Testing signal development on a bit line in an sram

Abstract

An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected. A binary logical value is written to a memory cell in the SRAM. The single dummy word line and a word line containing the memory cell in the SRAM are driven to logical high values concurrently. A dummy bit line, driven by the dummy memory cells, drives an input of a buffer to a binary logical value stored in the dummy memory cells. An output of the buffer enables a sense amp to amplify a voltage developed across the bit lines electrically connected to the memory cell.

What is claimed is: 
     
         1 . An electronic device for testing the signal development time of a selected memory cell in a static random access memory (SRAM) comprising:
 a single dummy word line wherein a first plurality of dummy memory cells are electrically connected to the single dummy word line;   a dummy bit line pair comprising a first dummy bit line and a second dummy bit line wherein a second plurality of dummy memory cells is connected to the dummy bit line pair;   a buffer having at least one input and at least one output; wherein the at least one input is electrically connected to one of the dummy bit lines; wherein the output of the buffer is electrically connected to a sense amp electrically connected to the selected memory cell;   wherein a number of dummy memory cells from the first plurality of dummy cells electrically drive the dummy bit line pair when the dummy word line is driven to a logical high value;   wherein a word line that is electrically connected to the selected memory cell is driven to a logical high value concurrently with the single dummy word line being driven to a logical high value.   
     
     
         2 . The electronic device of  claim 1  wherein the number of dummy memory cells from the first plurality of dummy cells is determined by a logical block. 
     
     
         3 . An electronic device for selecting the amount of time for signal development in a static random access memory (SRAM) comprising:
 a single dummy word line wherein a first plurality of dummy memory cells are electrically connected to the single dummy word line;   a dummy bit line pair comprising a first dummy bit line and a second dummy bit line wherein a second plurality of dummy memory cells is connected to the dummy bit line pair;   a buffer having at least one input and at least one output; wherein the at least one input is electrically connected to one of the dummy bit lines; wherein the output of the buffer is electrically connected to a sense amp electrically connected to the selected memory cell;   wherein a number of dummy memory cells from the first plurality of dummy cells electrically drive the dummy bit line pair when the single dummy word line is driven to a logical high value;   wherein a word line that is electrically connected to the selected memory cell is driven to a logical high value concurrently with the single dummy word line being driven to a logical high value.   
     
     
         4 . The electronic device of  claim 3  wherein the number of dummy memory cells from the first plurality of dummy cells is determined by a logical block.