Semiconductor device and method of manufacturing the same

Abstract

A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

What is claimed is: 
     
         1 . A chip comprising:
 a first MOSFET including terminals aligned with one another in a first direction;   a second MOSFET including terminals aligned with one another in the first direction;   a diode between the first and the second MOSFETs, the diode including terminals aligned with one another in either the first direction or second direction that is orthogonal to the first direction.   
     
     
         2 . The chip according to  claim 1 ,
 wherein the terminals of the diode include a first terminal and a second terminal, the first terminal and the second terminal are aligned in the first direction and are formed between a first region that includes the first MOSFET and a second region that includes the second MOSFET.   
     
     
         3 . The chip according to  claim 2 ,
 wherein the diode is formed at a lower portion of the first terminal in a cross-sectional view.   
     
     
         4 . The chip according to  claim 2 ,
 wherein the diode is divided into a lower portion of the first terminal and a lower portion of the second terminal.   
     
     
         5 . The chip according to  claim 2 ,
 wherein the terminals of the first MOSFET include a first source terminal and a first gate terminal, and the terminals of the second MOSFET include a second source terminal and a second gate terminal,   wherein the first source terminal and the second source terminal are arranged facing each other while sandwiching a boundary of the first region and the second region,   wherein the first gate terminal and the second gate terminal are arranged facing each other while sandwiching the boundary of the first region and the second region,   wherein the first terminal is formed between the first source terminal and the second source terminal, and   wherein the second terminal is formed between the first gate terminal and the second gate terminal.   
     
     
         6 . The chip according to  claim 5 ,
 wherein a distance between the first source terminal and the first terminal, and a distance between the second source terminal and the first terminal are substantially equal to each other, and   wherein a distance between the first gate terminal and the second terminal, and a distance between the second gate terminal and the second terminal are substantially equal to each other.   
     
     
         7 . The chip according to  claim 6 ,
 wherein a distance between the first source terminal and the first gate terminal, a distance between the second source terminal and the second gate terminal, and a distance between the first terminal and the second terminal are substantially equal to one another.   
     
     
         8 . The chip according to  claim 2 , further comprising a protection diode coupled in parallel with the diode and coupled with a polarity that opposes a polarity of the diode. 
     
     
         9 . The chip according to  claim 8 ,
 wherein the diode is formed at a lower portion of the first terminal, and   wherein the protection diode is formed at a lower portion of the second terminal.   
     
     
         10 . The chip according to  claim 1 ,
 wherein the terminals of the diode include a first terminal and a second terminal,   wherein the first terminal and the second terminal are aligned in the second direction,   the diode is formed between a first region that includes the first MOSFET and a second region that includes the second MOSFET, and   the first terminal is formed over the first region, and the second terminal is formed over the second region.   
     
     
         11 . The chip according to  claim 10 ,
 wherein the terminals of the first MOSFET include a first source terminal and a first gate terminal, and the terminals of the second MOSFET include a second source terminal and a second gate terminal,   wherein the first terminal is arranged so as to be sandwiched between the first source terminal and the first gate terminal, and   wherein the second terminal is arranged so as to be sandwiched between the second source terminal and the second gate terminal.   
     
     
         12 . The chip according to  claim 1 ,
 wherein the terminals of the first MOSFET include a first source terminal and a first gate terminal, and the terminals of the second MOSFET include a second source terminal and a second gate terminal,   wherein the first source terminal and the second gate terminal are arranged facing each other while sandwiching a boundary of a first region that includes the first MOSFET and a second region that includes the second MOSFET,   wherein the first gate terminal and the second source terminal are arranged facing each other while sandwiching the boundary of the first region and the second region, and   wherein the diode is arranged between the first region and the second region.   
     
     
         13 . The chip according to  claim 1 ,
 wherein the terminals of the diode include a first terminal and a second terminal,   wherein the diode is concentrically configured, with the first terminal being as a center.   
     
     
         14 . The chip according to  claim 13 ,
 wherein the diode comprises:   a plurality of connection structures including a first conductive type semiconductor layer and a second conductive type semiconductor layer; and   a plurality of contact metals formed between adjacent connection structures, for forming the diode.   
     
     
         15 . The chip according to  claim 14 ,
 wherein the first conductive type semiconductor layer comprises:   a first impurity concentration region formed on a second conductive type semiconductor layer side; and   a second impurity concentration region that is formed on a contact side, and that has a higher impurity concentration than that of the first impurity concentration region.   
     
     
         16 . The chip according to  claim 14 ,
 wherein a contact metal from among the plurality of contact metals has a height substantially equal to that of the first conductive type semiconductor layer and the second conductive type semiconductor layer.   
     
     
         17 . The semiconductor device according to  claim 1 ,
 wherein a bidirectional Zener diode is provided between gates and sources of the first MOSFET and the second MOSFET, respectively.