All digital burst-mode clock and data recovery (cdr)

Abstract

The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.

1 . A clock and data recovery (CDR) unit comprising:
 a bang-bang phase detector to receive data and to receive a recovered clock from a phase selector multiplexer and to produce a late and an early comparison output;   a block to receive the late and early comparison outputs and produce a Grey code output;   the phase selector multiplexer to select a clock phase as the recovered clock signal using the Grey code output.   
     
     
         2 . The clock and data recovery unit of  claim 1 , wherein the block increments the Grey code output when the early output is high and the late output is low. 
     
     
         3 . The clock and data recovery unit of  claim 2 , wherein the block decrements the Grey code output when the early output is low and the late output is high. 
     
     
         4 . The clock and data recovery unit of  claim 3 , wherein when the block implements a fixed phase recovery operation when the early and late outputs are both high. 
     
     
         5 . The clock and data recovery data unit of  claim 4 , wherein the fixed phase recovery operation includes advancing the Grey code output for a fixed number of periods greater than one, then returning to normal operation. 
     
     
         6 . The clock and data recovery data unit of  claim 5 , wherein the fixed number of periods is four or more. 
     
     
         7 . The clock and data recovery unit of  claim 1 , wherein the unit does not use a voltage controlled oscillator (VCO). 
     
     
         8 . The clock and data recovery unit of  claim 1 , wherein the CDR unit locks the recovered clock to the data within 3 clock cycles. 
     
     
         9 . The clock and data recovery unit of  claim 1 , wherein the signals through the clock and data recovery unit are such that the switching of the multiplexer does not produce glitches. 
     
     
         10 . The clock and data recovery unit of  claim 1 , wherein the data is USB input data. 
     
     
         11 . A clock and data recovery (CDR) unit comprising:
 a phase detector to receive data and to receive a recovered clock from a phase selector and to produce a late and early comparison output;   a block to receive the early and late output and produce a multiplexer selector control signal, the multiplexer selector control signal being incremented when the early signal is high and the late signal is low, the multiplexer selector control signal being decremented when the late signal is high and the early signal is low, and the block implementing a fixed phase recovery operation when both the early and late signals are high; and   the phase selector multiplexer to use the multiplexer selector control signal to select a clock phase as the recovered clock signal.   
     
     
         12 . The clock and data recovery data unit of  claim 11 , wherein the fixed phase recovery operation includes advancing the multiplexer selector control signal count for a fixed number of periods greater than one, then returning to normal operation. 
     
     
         13 . The clock and data recovery data unit of  claim 12 , wherein the fixed number periods is four or more. 
     
     
         14 . The clock and data recovery unit of  claim 11 , wherein the unit does not use a voltage controlled oscillator (VCO). 
     
     
         15 . The clock and data recovery unit of  claim 11 , wherein the CDR unit locks the recovered clock to the data within 3 clock cycles. 
     
     
         16 . The clock and data recovery unit of  claim 11 , wherein the signals through the clock and data recovery unit are such that the switching of the multiplexer does not produce glitches. 
     
     
         17 . The clock and data recovery unit of  claim 11 , wherein the data is USB input data. 
     
     
         18 . The clock and data recovery unit of  claim 11 , wherein the multiplexer selector control signal is a Grey code. 
     
     
         19 . The clock and data recovery unit of  claim 11 , wherein the phase detector is a bang-bang phase detector. 
     
     
         20 . The clock and data recovery unit of  claim 11 , further comprising a very early and a very late comparison output of the phase detector; the block further implementing a fixed multi-period operation when the very early or the very late output is high. 
     
     
         21 . The clock and data recovery unit of  claim 11 , wherein the number of selectable phases is four or more. 
     
     
         22 . The clock and data recovery unit of  claim 21 , wherein the number of selectable phases is ten.