Methods for etching dielectric materials in the fabrication of integrated circuits

Abstract

Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material.

What is claimed is: 
     
         1 . A method for fabricating an integrated circuit comprising:
 forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate, the gate electrode structure comprising a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface;   forming a layer of a second dielectric material over the layer of the first dielectric material, wherein the first dielectric material is different in composition than the second dielectric material; and   applying an etchant to the layer of the second material that fully removes the layer of the second material from the sidewall vertical surfaces of the gate electrode while only partially removing the layer of the second material from the horizontal top surface of the gate electrode structure and while leaving the layer of the first dielectric material substantially intact.   
     
     
         2 . The method of  claim 1 , wherein forming the layer of the first material comprises depositing the layer of the first material using chemical vapor deposition. 
     
     
         3 . The method of  claim 1 , wherein forming the layer of the second material comprises depositing the layer of the second material using chemical vapor deposition. 
     
     
         4 . The method of  claim 1 , wherein applying the etchant comprises applying a wet etchant. 
     
     
         5 . The method of  claim 1 , wherein applying the etchant further comprises partially removing the layer of the second dielectric material from horizontal surfaces of the semiconductor substrate adjacent to the gate electrode structure. 
     
     
         6 . The method of  claim 1 , wherein forming the layer of the first dielectric material comprises forming a layer of a silicon oxide material. 
     
     
         7 . The method of  claim 6 , wherein forming the layer of the second dielectric material comprises forming a layer of a silicon nitride material. 
     
     
         8 . The method of  claim 7 , wherein forming the layer of the silicon nitride material comprises depositing a silicon nitride material using non-conformal deposition techniques so that a thickness of the silicon nitride material on the horizontal top surface of the gate electrode structure is thicker than a thickness of the silicon nitride material on the sidewall vertical surfaces of the gate electrode structure. 
     
     
         9 . The method of  claim 8 , wherein applying the etchant comprises applying a solution of dilute hydrogen fluoride. 
     
     
         10 . The method of  claim 8 , wherein applying the etchant comprises applying a solution of phosphoric acid. 
     
     
         11 . The method of  claim 1 , wherein forming the layer of the first dielectric material comprises forming a layer of a silicon nitride material. 
     
     
         12 . The method of  claim 11 , wherein forming the layer of the second dielectric material comprises forming a layer of a silicon oxide material. 
     
     
         13 . The method of  claim 12 , wherein forming the layer of the silicon oxide material comprises forming the layer of silicon oxide with a first density along the sidewall vertical surfaces of the gate electrode structure and with a second density that is greater than the first density along the horizontal top surface of the gate electrode structure. 
     
     
         14 . The method of  claim 13 , wherein applying the etchant comprises applying a solution of hydrogen fluoride. 
     
     
         15 . A method for fabricating an integrated circuit comprising:
 conformally depositing a layer of a silicon dioxide over a gate electrode structure formed on a semiconductor substrate, the gate electrode structure comprising a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface;   non-conformally depositing a layer of silicon nitride over the layer of silicon dioxide in a manner such that a thickness of the silicon nitride material on the horizontal top surface of the gate electrode structure is thicker than a thickness of the silicon nitride material on the sidewall vertical surfaces of the gate electrode structure; and   applying a hydrogen fluoride etchant at a temperature of about 40° C. to about 100° C. or phosphoric acid etchant at a temperature of about 100° C. to about 185° C. to the layer of the silicon nitride to remove all of the silicon nitride from the sidewall vertical surfaces but only some of the silicon nitride from the horizontal top surface.   
     
     
         16 . The method of  claim 15 , wherein non-conformally depositing the layer of the silicon nitride comprises blanket depositing the layer of the silicon nitride using chemical vapor deposition. 
     
     
         17 . The method of  claim 15 , wherein conformally depositing the layer of the silicon dioxide comprises depositing the layer of the silicon dioxide using chemical vapor deposition. 
     
     
         18 . A method for fabricating an integrated circuit comprising:
 conformally depositing a layer of a silicon nitride over a gate electrode structure formed on a semiconductor substrate, the gate electrode structure comprising a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface;   conformally depositing a layer of silicon dioxide over the layer of silicon nitride in a manner such that a density of portions of the silicon dioxide layer deposited along the sidewall vertical surfaces has a density that is about 0.5 to about 0.75 as dense as a density of the silicon dioxide deposited along the horizontal top surface; and   applying a HF etchant to the layer of the silicon dioxide, the etchant having a temperature from about 20° C. to about 30° C. and a molar concentration of about 0.1 to about 5, the HF etchant being selective to the silicon dioxide layer over the silicon nitride layer, to remove all of the silicon dioxide from the sidewall vertical surfaces but only some of the silicon dioxide from the horizontal top surface.   
     
     
         19 . The method of  claim 18 , wherein conformally depositing the layer of the silicon nitride comprises depositing the layer of the silicon nitride using chemical vapor deposition. 
     
     
         20 . The method of  claim 18 , wherein conformally depositing the layer of the silicon dioxide comprises depositing the layer of the silicon dioxide using chemical vapor deposition.