Semiconductor wafer structure having si material and iii-n material on the (111) surface of the si material

Abstract

A semiconductor wafer structure includes a substrate, Si material on the substrate, the Si material having a thickness of 100 μm or less and a (111) surface facing away from the substrate, and III-N material on the (111) surface of the Si material. The substrate has a coefficient of thermal expansion more closely matched to that of the III-N material than the Si material. A GaN wafer having GaN material and a method of manufacturing an III-N substrate are also provided.

What is claimed is: 
     
         1 . A semiconductor wafer structure, comprising:
 a substrate;   Si material on the substrate, the Si material having a thickness of 100 μm or less and a (111) surface facing away from the substrate; and   III-N material on the (111) surface of the Si material,   wherein the substrate has a coefficient of thermal expansion more closely matched to that of the III-N material than the Si material.   
     
     
         2 . The semiconductor wafer structure of  claim 1 , wherein the Si material has a thickness of 10 μm or less. 
     
     
         3 . The semiconductor wafer structure of  claim 1 , wherein the III-N material comprises GaN and has a thickness of at least 10 μm. 
     
     
         4 . The semiconductor wafer structure of  claim 1 , further comprising a plurality of trenches extending from the (111) surface into the Si material. 
     
     
         5 . The semiconductor wafer structure of  claim 4 , wherein the trenches are filled with a material. 
     
     
         6 . The semiconductor wafer structure of  claim 5 , wherein the material is a dielectric. 
     
     
         7 . The semiconductor wafer structure of  claim 4 , wherein the trenches segment the Si material into islands of Si material separated from each other by the trenches. 
     
     
         8 . The semiconductor wafer structure of  claim 4 , wherein the substrate is separated from a bottom of the trenches by an additional layer of Si. 
     
     
         9 . The semiconductor wafer structure of  claim 4 , wherein the trenches are wider than the Si material between the trenches. 
     
     
         10 . The semiconductor wafer structure of  claim 4 , wherein the trenches are filled with at least two different materials. 
     
     
         11 . The semiconductor wafer structure of  claim 10 , wherein an inner part of the trenches is filled with an electrically conductive material and an outer part of the trenches surrounding the inner part is filled with an electrically insulating material. 
     
     
         12 . A method of manufacturing an III-N substrate, the method comprising:
 providing a first substrate having a first surface and a second surface opposing the first surface;   forming an III-N material of a first thickness on the first surface of the first substrate;   removing the first substrate after the III-N material is formed at the first thickness;   bonding a second substrate to a side of the III-N material, the second substrate having a coefficient of thermal expansion more closely matched to that of the III-N material than the first substrate; and   increasing the thickness of the III-N material to a second thickness greater than the first thickness after the first substrate is removed and the second substrate is bonded to the III-N material, the first thickness being sufficient to ensure that the second substrate has no influence on the crystal structure of the III-N material when the thickness of the III-N material is increased from the first thickness to the second thickness.   
     
     
         13 . The method of  claim 12 , wherein the first substrate comprises Si, the first surface of the first substrate is a (111) Si surface, and the III-N material comprises GaN and one or more buffer layers formed on the (111) Si surface. 
     
     
         14 . The method of  claim 12 , wherein bonding the second substrate to an exposed side of the III-N material comprises:
 bonding a third substrate to a side of the III-N material facing away from the first substrate;   removing the first substrate after the third substrate is bonded to the III-N material to expose a side of the III-N material previously covered by the first substrate; and   bonding the second substrate to the exposed side of the III-N material.   
     
     
         15 . The method of  claim 12 , further comprising removing the second substrate from the III-N material after the thickness of the III-N material is increased to the second thickness. 
     
     
         16 . A GaN wafer comprising GaN material, the GaN material having a diameter of at least 200 mm and a thickness of at least 10 μm.