Semiconductor device

Abstract

A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a common source region formed in a semiconductor substrate;   a bit line formed over the semiconductor substrate;   first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate;   first stacked conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer;   second stacked conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer; and   a charge storage layer formed between the first vertical channel layer and the first stacked conductive layers and between the second vertical channel layer and the second stacked conductive layers.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the one side of the first vertical channel layer surrounded by the first stacked conductive layers is round, while the other side of the first vertical channel layer is flat. 
     
     
         3 . The semiconductor device of claim wherein the one side of the second vertical channel layer surrounded by the second stacked conductive layers is round, while the other side of the second vertical channel layer is flat. 
     
     
         4 . The semiconductor device of claim wherein the other sides of the first vertical channel layer and the second vertical channel layer face each other. 
     
     
         5 . The semiconductor device of  claim 1 , wherein uppermost conductive layers of the first stacked conductive layers and the second stacked conductive layers include drain selection lines, and
 lowermost conductive layers of the first stacked conductive layers and the second stacked conductive layers includes source selection lines, and   conductive layers stacked between the uppermost conductive layers and the lowermost conductive layers include word lines.   
     
     
         6 . A semiconductor device, comprising:
 first and second vertical channel layers vertically coupled between a semiconductor substrate and a bit line;   third and fourth vertical channel layers vertically coupled between the semiconductor substrate and a common source line;   first and second multilayer conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer and one side of the second vertical channel layer, respectively;   third and fourth multilayer conductive layers stacked over the semiconductor substrate to surround one side of the third vertical channel layer and one side of the fourth vertical channel layer, respectively;   first charge storage layers formed between the first to fourth vertical channel layers and the first to fourth multilayer conductive layers;   a first pipe channel layer formed in the semiconductor substrate to couple lower portions of the first and fourth vertical channel layers; and   a second pipe channel layer formed in the semiconductor substrate to couple lower portions of the second and third vertical channel layers.   
     
     
         7 . The semiconductor device of  claim 6 , wherein the one sides of the first to fourth vertical channel layers surrounded by the first to fourth multilayer conductive layers, respectively, are round, while the other sides of the first to fourth vertical channel layers are flat. 
     
     
         8 . The semiconductor device of  claim 6 , wherein the other sides of the first vertical channel layer and the second vertical channel layer face each other, and
 the other sides of the third vertical channel layer and the fourth vertical channel layer face each other.   
     
     
         9 . The semiconductor device of  claim 6 , wherein the first pipe channel layer is formed under the second pipe channel layer. 
     
     
         10 . The semiconductor device of  claim 6 , wherein uppermost conductive layers of the first and third multilayer conductive layers are separate from uppermost conductive layers of the second and fourth multilayer conductive layers, respectively, while the other conductive layers of the first and third multilayer conductive layers are coupled to the other conductive layers of the second and fourth multilayer conductive layers, respectively. 
     
     
         11 . The semiconductor device of  claim 6 , wherein uppermost conductive layers of the first multilayer conductive layers and the second multilayer conductive layers include drain selection lines, and
 uppermost conductive layers of the third multilayer conductive layers and the fourth multilayer conductive layers include source selection lines, and   the other conductive layers of the first to fourth multilayer conductive layers include word lines.   
     
     
         12 . The semiconductor device of claim b, further comprising:
 fifth and sixth vertical channel layers vertically coupled between the semiconductor substrate and the common source line;   seventh and eighth vertical channel layers vertically coupled between the semiconductor substrate and the bit line;   fifth and sixth multilayer conductive layers stacked over the semiconductor substrate to surround one side of the fifth vertical channel layer and one side of the sixth vertical channel layer, respectively;   seventh and eighth multilayer conductive layers stacked over the semiconductor substrate to surround one side of the seventh vertical channel layer and one side of the eighth vertical channel layer, respectively;   second charge storage layers formed between the fifth to eighth vertical channel layers and the fifth to eighth multilayer conductive layers;   a third pipe channel layer formed in the semiconductor substrate to couple lower portions of the fifth and eighth vertical channel layers; and   a fourth pipe channel layer formed in the semiconductor substrate to couple lower portions of the sixth and seventh vertical channel layers.   
     
     
         13 . The semiconductor device of  claim 12 , wherein other conductive layers than uppermost conductive layers of the first and second multilayer conductive layers are coupled to other conductive layers than uppermost conductive layers of the seventh and eighth multilayer conductive layers, respectively, and
 other conductive layers than uppermost conductive layers of the third multilayer conductive layers are coupled to other conductive layers than uppermost conductive layers of the sixth multilayer conductive layers, respectively.   
     
     
         14 . A semiconductor device, comprising:
 first, second, fifth and sixth vertical channel layers vertically coupled between a semiconductor substrate and a bit line;   third, fourth, seventh and eighth vertical channel layers vertically coupled between the semiconductor substrate and a common source line;   first, third, fifth and seventh multilayer conductive layers stacked on the semiconductor substrate at predetermined distances to surround one side of the first, third, fifth and seventh vertical channel layers, respectively;   second, fourth, sixth and eighth multilayer conductive layers stacked on the semiconductor substrate at predetermined distances to surround one side of the second, fourth, sixth and eighth vertical channel layers respectively;   charge storage layers formed between the first to eighth vertical channel layers and the first to eighth multilayer conductive layers;   a first pipe channel layer formed in the semiconductor substrate to couple lower portions of the first and eighth vertical channel layers;   a second pipe channel layer formed in the semiconductor substrate to couple lower portions of the second and third vertical channel layers;   a third pipe channel layer formed in the semiconductor substrate to couple lower portions of the fourth and fifth vertical channel layers; and   a fourth pipe channel layer formed in the semiconductor substrate to couple lower portions of the sixth and seventh vertical channel layers.   
     
     
         15 . The semiconductor device of  claim 14 , wherein the one side of the first to eighth vertical channel layers surrounded by the first to eighth multilayer conductive layers, respectively, are round, while the other sides of the first to eighth vertical channel layers are flat. 
     
     
         16 . The semiconductor device of  claim 14 , wherein the other sides of the first vertical channel layer and the second vertical channel layer face each other, and
 the other sides of the third vertical channel layer and the fourth vertical channel layer face each other, and   the other sides of the fifth vertical channel layer and the sixth vertical channel layer face each other, and   the other sides of the seventh vertical channel layer and the eighth vertical channel layer face each other.   
     
     
         17 . The semiconductor device of  claim 14 , wherein other conductive layers than uppermost conductive layers of the first to eighth multilayer conductive layers include word lines, and
 the word lines of the first, second, third, and fourth multilayer conductive layers are coupled to the word lines of the fifth, sixth, seventh, and eighth multilayer conductive layers, respectively, while the uppermost conductive layers of the first to eighth multilayer conductive layers are separate from each other.   
     
     
         18 . The semiconductor device of  claim 14 , wherein the first to eighth vertical channel layers are sequentially arranged on the semiconductor substrate. 
     
     
         19 . The semiconductor device of  claim 14 , wherein uppermost conductive layers of the first, second, fifth and sixth multilayer conductive layers include drain selection lines, and
 uppermost conductive layers of the third, fourth, seventh and eighth multilayer conductive layers include source selection lines, and   remaining conductive layers of the first to eighth multilayer conductive layers include word lines.