Semiconductor Device Package and Method of the Same

Abstract

The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

What is claimed is: 
     
         1 . A method for forming a semiconductor device package, comprising:
 preparing a first substrate and a second substrate, wherein said first substrate includes a wiring circuit and an aligning mark disposed on a top surface thereof and a contact conductive bump is formed on said wiring circuit;   opening a die opening window through said second substrate by using a laser or punching method;   preparing an adhesive material;   attaching said second substrate to said first substrate by said adhesive material such that said adhesive material is disposed between said top surface of said first substrate and a bottom surface of said second substrate to directly attach said second substrate onto said first substrate;   aligning a die with a bump structure on the bonding pads of said die by using said aligning mark and attaching said die onto said contact conductive bump with force by said adhesive material such that said bump structure of said die is electrically connected to said contact conductive bump of said wiring circuit of said first substrate;   forming a dielectric layer on a top surface of said second substrate and said die and pushing said dielectric layer into a gap between a side wall of said die and a side wall of said die opening window;   opening a plurality of via openings in said dielectric layer; and   forming a redistribution layer in said plurality of via openings and on said dielectric layer.   
     
     
         2 . The method of  claim 1 , further comprising a step of forming a cover layer on a top surface of said dielectric layer and a top surface of said redistribution layer. 
     
     
         3 . A method for forming a semiconductor device package, comprising:
 preparing carrier tools with alignment mark   setting a first substrate with first wiring circuits on both site and an adhesive layer on a top surface of said first substrate, and aligning said first substrate on said carrier tool with said alignment mark matching;   setting a second substrate with second wiring circuits on both site and a die open area, and aligning and placing said second substrate on said adhesive layer of said first substrate;   aligning and placing a die with metallization bump structure into said die open area and attached on said adhesive layer of said first substrate;   bonding said first substrate with adhesive layer, said substrate and said die by a panel bonder together with said carrier tools to adhere said first substrate, said second substrate and said die together and re-flowing said metallization bump for electrical inter-connecting between said first substrate, said second substrate and said die.