Lcd panel driving circuit, lcd device, and driving method

Abstract

A liquid crystal display (LCD) panel driving circuit includes at least two signal input interfaces, one or more timing control circuits, a memory module, and a data processing module. When the memory module receives image data of a same display image from the signal input interfaces, the data processing module reads the image data from the memory module, the data processing module sends the image data to the one or more timing control circuits, and the one or more timing control circuits drive the LCD panel using the image data.

1 . A liquid crystal display (LCD) panel driving circuit, comprising:
 at least two signal input interfaces;   one or more timing control circuits,   a memory module; and   a data processing module;   when the memory module receives image data of a same display image from the signal input interfaces, the data processing module reads the image data from the memory module, the data processing module sends the image data to the one or more timing control circuits, and the one or more timing control circuits drive the LCD panel using the image data.   
     
     
         2 . The liquid crystal display (LCD) panel driving circuit of  claim 1 , wherein there are at least two timing control circuits; the data processing module reads the image data from the memory module and processes the image data, and simultaneously sends the image data to the timing control circuits. 
     
     
         3 . The liquid crystal display (LCD) panel driving circuit of  claim 1 , wherein the data processing module comprises a converting unit that converts the image data into a readable data format of the one or more timing control circuits. 
     
     
         4 . The liquid crystal display (LCD) panel driving circuit of  claim 1 , wherein the memory module comprises at least two storage spaces, and each of the storage spaces stores the image data of one signal input interface; when each of the storage spaces is stored with the image data, the data processing module simultaneously reads the image data of each of the storage spaces, and sends the image data to the one or more timing control circuits. 
     
     
         5 . The liquid crystal display (LCD) panel driving circuit of  claim 1 , wherein there are at least two timing control circuits; the data processing module comprises a converting unit that converts the image data into a readable data format of the timing control circuits; the memory module comprises at least two storage spaces, and each of the storage spaces stores the image data of one signal input interface; when each of the storage spaces is stored with the image data, the data processing module simultaneously reads the image data of each of the storage spaces, and sends the image data to the timing control circuits. 
     
     
         6 . The liquid crystal display (LCD) panel driving circuit of  claim 1 , wherein the image data of the storage spaces are transmitted to the data processing module line by line. 
     
     
         7 . The liquid crystal display (LCD) panel driving circuit of  claim 1 , wherein the signal input interface is any one of a digital visual interface (DVI), a high definition multimedia interface (HDMI) or a high definition digital display interface; the data processing module is a field-programmable gate array (FPGA). 
     
     
         8 . A liquid crystal display (LCD) device, comprising:
 an LCD panel driving circuit comprising at least two signal input interfaces, one or more timing control circuits, a memory module, and a data processing module;   when the memory module receives image data of a same display image from the signal input interfaces, the data processing module reads the image data from the memory module, the data processing module sends the image data to the one or more timing control circuits, and the one or more timing control circuits drive the LCD panel using the image data.   
     
     
         9 . The liquid crystal display (LCD) device of  claim 8 , wherein there are at least two timing control circuits; the data processing module reads the image data from the memory module and processes the image data, and simultaneously sends the image data to the timing control circuits. 
     
     
         10 . The liquid crystal display (LCD) device of  claim 8 , wherein the data processing module comprises a converting unit that converts the image data into a readable data format of the one or more timing control circuits. 
     
     
         11 . The liquid crystal display (LCD) device of  claim 8 , wherein the memory module comprises at least two storage spaces, and each of the storage spaces stores the image data of one signal input interface; when each of the storage spaces is stored with the image data, the data processing module simultaneously reads the image data of each of the storage spaces, and sends the image data to the one or more timing control circuits. 
     
     
         12 . The liquid crystal display (LCD) device of  claim 8 , wherein there are at least two timing control circuits; the data processing module comprises a converting unit that converts the image data into a readable data format of the timing control circuits; the memory module comprises at least two storage spaces, and each of the storage spaces stores the image data of one signal input interface; when each of the storage spaces is stored with the image data, the data processing module simultaneously reads the image data of each of the storage spaces, and sends the image data to the timing control circuits. 
     
     
         13 . The liquid crystal display (LCD) device of  claim 8 , wherein the image data of the storage spaces are transmitted to the data processing module line by line. 
     
     
         14 . The liquid crystal display (LCD) device of  claim 8 , wherein the signal input interface is any one of a digital visual interface (DVI), a high definition multimedia interface (HDMI) or a high definition digital display interface; the data processing module is a field-programmable gate array (FPGA). 
     
     
         15 . A multiple-channel signal input liquid crystal display (LCD) panel driving method, comprising the following steps:
 A. waiting for image data input from signal input interfaces of an LCD panel driving circuit, and storing the image data into a memory module of the LCD panel driving circuit;   B. going to step C when all of the signal input interfaces are stored with a same image data in the memory module; if not all of the signal input interfaces are stored with the same image data in the memory module, return to step A;   C. driving an LCD panel when all of current image data are simultaneously sent to one or more timing control circuits of the LCD panel driving circuit.   
     
     
         16 . The multiple-channel signal input LCD panel driving method of  claim 15 , wherein there are at least two timing control circuits; the step A comprises:
 establishing a same number of storage spaces as a number of the signal input interfaces in the memory module; writing the image data of the two signal input interfaces into the corresponding two storage spaces, respectively; the step B comprises: detecting contents of the two storage spaces; if the contents of the two storage spaces are both not empty, going to the step C, if contents of either of the storage space is detected to be empty, returning to the step A;   the step C comprises: using a data processing module of the LCD panel driving circuit to read the image data from the memory module, converting the image data into a readable data format of the timing control circuits, and sending the image data in the readable data format to the timing control circuits.