Trench forming method, metal wiring forming method, and method of manufacturing thin film transistor array panel

Abstract

A method of forming a thin film transistor array panel includes: forming a first insulating layer on a substrate; forming an amorphous carbon layer on the first insulating layer; forming a second insulating layer on the amorphous carbon layer; forming an opening in the amorphous carbon layer by patterning the second insulating layer and the amorphous carbon layer; and forming a trench in the first insulating layer by etching the first insulating layer, the etching the first insulating layer using the amorphous carbon layer including the opening as a mask.

What is claimed is: 
     
         1 . A method of forming a thin film transistor array panel, the method comprising:
 providing a first insulating layer on a substrate;   providing an amorphous carbon layer on the first insulating layer;   providing a second insulating layer on the amorphous carbon layer;   patterning the second insulating layer and the amorphous carbon layer, to form an opening in the amorphous carbon layer;   etching the first insulating layer by using the amorphous carbon layer comprising the opening as a mask, to form a trench in the first insulating layer;   removing the amorphous carbon layer;   providing a metal layer on the substrate; and   polishing the metal layer through a chemical mechanical polishing process, to form a metal wiring in the trench.   
     
     
         2 . The method of  claim 1 , wherein:
 the metal wiring comprises copper.   
     
     
         3 . The method of  claim 2 , wherein:
 the first insulating layer comprises one of SiN, SiO, SiC, SiOC, or SiON, and   the second insulating layer comprises at least one of SiN, SiO, or SiON.   
     
     
         4 . The method of  claim 2 , wherein:
 the providing the opening comprises:
 providing a photosensitive film on the second insulating layer, and exposing and developing the photosensitive film, to pattern the photosensitive film; 
 etching the second insulating layer by using the patterned photosensitive film as a mask; 
 etching the amorphous carbon layer by using the second insulating layer as a mask, to form the opening; and 
 removing the photosensitive film. 
   
     
     
         5 . The method of  claim 4 , wherein:
 in the etching the second insulating layer of the providing the opening and in the etching the first insulating layer of the providing the trench,   the second insulating layer and the first insulating layer are etched by using a first primary etching gas, the first primary etching gas comprising fluorine, and   in the etching of the amorphous carbon layer,   the amorphous carbon layer is etched by using a second primary etching gas and an assistant etching gas,   the second primary etching gas comprising oxygen, and the assistant etching gas comprising at least one of hydrogen bromide or argon.   
     
     
         6 . The method of  claim 2 , wherein:
 the providing the amorphous carbon layer comprises a chemical vapor deposition process,   the chemical vapor deposition process uses a gas, the gas comprising carbon and hydrogen, and   the gas comprising carbon and hydrogen comprises at least one of C 2 H 4 , C 3 H 6 , or C 4 H 8 .   
     
     
         7 . A method of manufacturing a thin film transistor array panel, the method comprising:
 providing a first insulating layer on a substrate;   providing an amorphous carbon layer on the first insulating layer;   providing a second insulating layer on the amorphous carbon layer;   patterning the second insulating layer and the amorphous carbon layer to form an opening in the amorphous carbon layer;   etching the first insulating layer by using the amorphous carbon layer comprising the opening as a mask, to form a trench in the first insulating layer;   removing the amorphous carbon layer;   providing a metal layer on the substrate;   polishing the metal layer through a chemical mechanical polishing process, to form a gate electrode in the trench;   providing a gate insulating film on the gate electrode;   providing a semiconductor layer on the gate insulating film;   providing a source electrode and a drain electrode on the semiconductor layer, the source electrode and the drain electrode spaced apart from each other;   providing a passivation film on the source electrode and the drain electrode;   providing a contact hole in the passivation film, the contact hole exposing a portion of the drain electrode; and   providing a pixel electrode on the passivation film, the pixel electrode connected to the drain electrode through the contact hole.   
     
     
         8 . The method of  claim 7 , wherein:
 the metal wiring comprises copper,   the first insulating layer comprises at least one of SiN, SiO, SiC, SiOC, or SiON, and   the second insulating layer comprises at least one of SiN, SiO, or SiON.