Memory and process sharing via input/output with virtualization

Abstract

Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system.

What is claimed is: 
     
         1 . A circuit having multiple chipsets, comprising:
 a first chipset having a first processor and a first memory unit;   a second chipset having a second processor and a second memory unit;   a third chipset having a third processor and a third memory unit; and   a communication channel coupling the first chipset, the second chipset, and the third chipset to each other; and   wherein the first processor is configured to disengage the first memory unit and to access the third memory unit, and wherein the second processor is configured to disengage the second memory unit based and to access the third memory unit.   
     
     
         2 . The circuit of  claim 1 , wherein the first processor, second processor and the third processor are configured to communicate with a main controller. 
     
     
         3 . The circuit of  claim 2 , the first processor, second processor, and the third processor each comprising:
 an input/output (I/O) unit;   a core unit coupled to the I/O unit;   a cache unit coupled to the core unit; and   a memory controller coupled to the cache unit.   
     
     
         4 . The circuit of  claim 3 , the I/O unit having direct memory access (DMA) for internal and external services. 
     
     
         5 . The circuit of  claim 3 , the core unit being configured to negotiate with the main controller to adjust a virtualized memory size and perform memory mapping for the circuit. 
     
     
         6 . The circuit of  claim 1 , wherein a multiple-to-one virtualized mapping is performed between the first chipset, second chipset, and the third chipset. 
     
     
         7 . The circuit of  claim 1 , wherein the first processor, the first memory unit, the second processor, and the second memory unit, and the third processor, and the third memory each have a separate power supply. 
     
     
         8 . The circuit of  claim 1 , wherein the third memory unit is larger than the second memory unit, and wherein the third memory unit is larger than the first memory unit. 
     
     
         9 . The circuit of  claim 8 , the first processor, the second processor, and the third processor each being configured to poll data within the circuit , and wherein the data is pertaining to at least one of the following: memory type, memory size, communication latency, data rate, available power, and memory utilization. 
     
     
         10 . The circuit of  claim 1 , wherein the first processor serves as a main controller. 
     
     
         11 . A system having multiple chipsets, comprising:
 a main controller;   a first chipset in communication with the main controller, the first chipset having a first processor coupled to a first power supply and a first memory unit coupled to a second power supply;   a second chipset in communication with the main controller, the second chipset having a second processor coupled to a third power supply and a second memory unit coupled to a fourth power supply;   a third chipset in communication with the main controller, the second chipset having a third processor coupled to a fifth power supply and a third memory unit coupled to a sixth power supply; and   a communication channel coupling the first chipset, the second chipset, and the third chipset to each other, and wherein the first processor is configured to disengage the first memory unit and to access the third memory unit, and wherein the second processor is configured to disengage the second memory unit and to access the third memory unit.   
     
     
         12 . The system of  claim 11 , the first processor, second processor, and third processor each comprising:
 an input/output (I/O) unit;   a core unit coupled to the I/O unit;   a cache unit coupled to the core unit; and   a memory controller coupled to the cache unit.   
     
     
         13 . The system of  claim 12 , the I/O unit having direct memory access (DMA) for internal and external services. 
     
     
         14 . The system of  claim 12 , the core unit being configured to negotiate with the main controller to adjust a virtualized memory size and perform memory mapping for the system. 
     
     
         15 . The system of  claim 11 , wherein processes and memory addresses are configured to perform a multiple-to-one virtualized mapping between the first chipset, second chipset, and the third chipset. 
     
     
         16 . The system of  claim 11 , the first processor, second processor, and third processor each being configured to poll data within the system. 
     
     
         17 . The system of  claim 16 , the data pertaining to at least one of the following: memory type, memory size, communication latency, data rate, available power, and memory utilization. 
     
     
         18 . The system of  claim 11 , wherein the first processor comprises the main controller. 
     
     
         19 . The system of  claim 11 , wherein the third memory unit is larger than the second memory unit, and wherein the third memory unit is larger than the first memory unit. 
     
     
         20 . The system of  claim 19 , wherein the first processor is configured to transfer memory contents from the first memory unit to the third memory unit prior to disengaging the first memory unit, and wherein the second processor is configured to transfer memory contents from the second memory unit to the third memory unit prior to disengaging the second memory unit.