Integrated circuits with stressed semiconductor substrates and processes for preparing integrated circuits including the stressed semiconductor substrates

Abstract

Integrated circuits with stressed semiconductor substrates, processes for preparing stressed semiconductor substrates, and processes for preparing integrated circuits including stressed semiconductor substrates are provided herein. An exemplary process for preparing a stressed semiconductor substrate includes providing a semiconductor substrate of a semiconductor material having a first crystalline lattice constant; introducing a dopant on and into a surface layer of the semiconductor substrate via ion implantation at an amount above a solubility limit of the dopant in the semiconductor material to form a dopant-containing surface layer of the semiconductor substrate; applying energy to the dopant-containing surface layer of the semiconductor substrate with an ultra-short pulse laser to form a molten semiconductor:dopant layer on a surface of the semiconductor substrate; and removing the energy such that the molten semiconductor:dopant layer forms a solid semiconductor:dopant layer with a second crystalline lattice having a second lattice constant that differs from the first lattice constant.

What is claimed is: 
     
         1 . A process for preparing a stressed semiconductor substrate, said process comprising:
 providing a semiconductor substrate of a semiconductor material having a first crystalline lattice with a first lattice constant;   introducing a dopant on and into a surface layer of the semiconductor substrate via ion implantation at an amount above a solubility limit of the dopant in the semiconductor material to form a dopant-containing surface layer of the semiconductor substrate;   applying energy to the dopant-containing surface layer of the semiconductor substrate with an ultra-short pulse laser to form a molten semiconductor:dopant layer on a surface of the semiconductor substrate; and   removing the energy such that the molten semiconductor:dopant layer forms a solid semiconductor:dopant layer with a second crystalline lattice having a second lattice constant that differs from the first lattice constant, thereby forming a stressed semiconductor substrate.   
     
     
         2 . The process of  claim 1 , wherein the ultra-short pulse laser has a pulse time of about 10 ns to 200 ns, and a fluence of about 1 J/cm 2  to 2 J/cm 2 . 
     
     
         3 . The process of  claim 1 , wherein the semiconductor material comprises a semiconductor material selected from the group consisting of silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). 
     
     
         4 . The process of  claim 1 , wherein the dopant is selected from the group consisting of boron (B), carbon (C), phosphorous (P), and nitrogen (N). 
     
     
         5 . The process of  claim 1 , wherein the solid semiconductor:dopant layer comprises about 3% to about 5% dopant substitution within the solid semiconductor:dopant layer crystalline lattice. 
     
     
         6 . The process of  claim 1 , wherein the second lattice constant is less than the first lattice constant. 
     
     
         7 . The process of  claim 1 , wherein the second lattice constant is greater than the first lattice constant. 
     
     
         8 . The process of  claim 1 , wherein the dopant is introduced on and into the surface layer of the semiconductor substrate via ion implantation at an energy of about 1 to about 10 K eV. 
     
     
         9 . The process of  claim 1 , wherein the semiconductor substrate comprises silicon and the dopant is boron. 
     
     
         10 . A process for preparing an integrated circuit including a stressed semiconductor substrate, said process comprising:
 providing a semiconductor substrate of a semiconductor material having a first crystalline lattice with a first lattice constant;   introducing a dopant on and into a surface layer of the semiconductor substrate via ion implantation at an amount above a solubility limit of the dopant in the semiconductor material to form a dopant-containing surface layer of the semiconductor substrate;   applying energy to the dopant-containing surface layer of the semiconductor substrate with an ultra-short pulse laser to form a molten semiconductor:dopant layer on a surface of the semiconductor substrate;   removing the energy such that the molten semiconductor:dopant layer forms a solid semiconductor:dopant layer with a second crystalline lattice having a second lattice constant that differs from the first lattice constant, thereby forming a stressed semiconductor substrate; and   forming a transistor in and on the stressed semiconductor substrate.   
     
     
         11 . The process of  claim 10 , wherein the ultra-short pulse laser has a pulse time of about 10 ns to 200 ns, and a fluence of about 1 J/cm 2  to 2 J/cm 2 . 
     
     
         12 . The process of  claim 10 , further comprising forming at least one level of interconnect routing over the transistor on the stressed semiconductor substrate. 
     
     
         13 . The process of  claim 10 , wherein the semiconductor substrate comprises a semiconductor material selected from the group consisting of silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). 
     
     
         14 . The process of  claim 10 , wherein the dopant is selected from the group consisting of boron (B), carbon (C), phosphorous (P), and nitrogen (N). 
     
     
         15 . The process of  claim 10 , wherein the solid semiconductor:dopant layer comprises about 3% to about 5% dopant substitution within the solid semiconductor:dopant layer crystalline lattice. 
     
     
         16 . The process of  claim 10 , wherein the second lattice constant is less than the first lattice constant. 
     
     
         17 . The process of  claim 10 , wherein the second lattice constant is greater than the first lattice constant. 
     
     
         18 . The process of  claim 10 , wherein the dopant is introduced on and into the surface layer of the semiconductor substrate via ion implantation at an energy of about 1 to about 10 K eV. 
     
     
         19 . The process of  claim 10 , wherein the semiconductor material is silicon and the dopant is boron. 
     
     
         20 . An integrated circuit comprising:
 a stressed semiconductor substrate comprising:
 a semiconductor material having a first crystalline lattice with a first lattice constant; and 
 a semiconductor:dopant layer disposed on the semiconductor material, wherein the semiconductor:dopant layer has a second crystalline lattice having a second lattice constant that differs from the first lattice constant, wherein the semiconductor:dopant layer has a thickness of less than about 5 nm; and 
   a transistor disposed in and on the semiconductor substrate.