Restore PCIe Transaction ID On The Fly

Abstract

Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.

1 . A system for direct memory access (DMA), the system comprising:
 a memory operable to maintain a DMA resource, wherein the DMA resource is associated with a first DMA operation, the DMA resource comprising a DMA identifier; and   a processor operable to reuse the DMA resource for a second DMA operation without requiring the processor to be reset.   
     
     
         2 - 25 . (canceled) 
     
     
         26 . The system of  claim 1 , wherein the DMA resource is reused without disturbing the first DMA operation. 
     
     
         27 . The system of  claim 1 , wherein the DMA resource is reused without impacting a new DMA operation. 
     
     
         28 . The system of  claim 1 , wherein the DMA resource is reused without impacting future commands that are in a queue for operation. 
     
     
         29 . The system of  claim 1 , wherein the DMA resource is reused without depending on a status of the first DMA operation. 
     
     
         30 . The system of  claim 1 , wherein the processor is operable to periodically poll the memory to determine when the DMA resource should be reused. 
     
     
         31 . The system of  claim 1 , wherein the DMA resource is reused based on an availability of another DMA resource. 
     
     
         32 . The system of  claim 1 , wherein the DMA resource is reused based on the number of additional DMA resources. 
     
     
         33 . The system of  claim 1 , wherein the DMA resource is reused based on a predetermined rate. 
     
     
         34 . The system of  claim 1 , wherein the processor is incorporated within a host bus adapter (HBA). 
     
     
         35 . A method for managing direct memory access (DMA), the method comprising:
 maintaining an individual status of each DMA resource of a plurality of DMA resources;   assigning a DMA resource of the plurality of DMA resources with a first DMA operation, the DMA resource comprising a DMA identifier; and   reusing the DMA resource for a second DMA operation without requiring a processor to be reset.   
     
     
         36 . The method of  claim 35 , wherein the DMA resource is reused without disturbing the first DMA operation. 
     
     
         37 . The method of  claim 35 , wherein the DMA resource is reused without impacting a new DMA operation. 
     
     
         38 . The method of  claim 35 , wherein the DMA resource is reused without impacting future commands that are in a queue for operation. 
     
     
         39 . The method of  claim 35 , wherein the DMA resource is reused without depending on a status of the first DMA operation. 
     
     
         40 . The method of  claim 35 , wherein the method comprises periodically polling to determine when the DMA resource should be reused. 
     
     
         41 . The method of  claim 35 , wherein the DMA resource is reused based on the number of unused DMA resources in the plurality of DMA resources. 
     
     
         42 . The method of  claim 35 , wherein the DMA resource is reused based the number of used DMA resources in the plurality of DMA resources. 
     
     
         43 . The method of  claim 35 , wherein the DMA resource is reused based on a predetermined rate. 
     
     
         44 . The method of  claim 35 , wherein the processor is incorporated within a host bus adapter (HBA).