Interposer frame with polymer matrix and methods of fabrication
Abstract
An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. In an embodiment, a panel includes an array of chip sockets, each surrounded and defined by an organic matrix framework including a grid of copper vias through the organic matrix framework. The panel includes at least a first region with sockets having a set of dimensions for receiving one type of chip and a second region with sockets and another set of dimensions for receiving a second type of chip.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework.
2 . The array of chip sockets of claim 1 , wherein each chip socket is surrounded with a frame of organic matrix including copper vias through the frame.
3 . The array of chip sockets of claim 1 , wherein the organic matrix framework further comprises glass fiber bundles.
4 . The array of chip sockets of claim 1 , wherein the copper vias are via posts.
5 . The array of chip sockets of claim 1 , wherein each via is in the range of 25 micron to 500 micron wide.
6 . The array of chip sockets of claim 1 , wherein each via is cylindrical and has a diameter in the range of 25 micron to 500 micron.
7 . The array of chip sockets of claim 7 wherein a frame around at least one socket comprises alternating via posts and feature layers and comprises at least one via post layer and one feature layer.
8 . The array of chip sockets of claim 1 wherein the grid of metal vias through the organic matrix framework comprises a plurality of via layers.
9 . The array of chip sockets of claim 7 wherein a frame around at least one socket comprises a continuous coil of alternating via posts and feature layers spanning at least one via post layer and one feature layer.
10 . The array of claim 7 wherein the via posts comprise elongated vias posts.
11 . The array of chip sockets of claim 9 wherein the continuous coil of elongated vias posts spans a plurality of via post layers.
12 . The array of chip sockets of claim 1 , comprising adjacent chip sockets of different dimensions.
13 . The array of chip sockets of claim 12 , comprising adjacent chip sockets of different size.
14 . The array of chip sockets of claim 12 , comprising adjacent chip sockets of different shape.
15 . A panel comprising an array of chip sockets, each surrounded and defined by an organic matrix framework comprising a grid of copper vias through the organic matrix framework, wherein said panel comprises at least one region having sockets with a first set of dimensions for receiving one type of chip, and a second region having sockets with a second set of dimensions for receiving a second type of chip.
16 . A method of fabricating an array of chip sockets surrounded by an organic matrix framework comprising:
obtaining a sacrificial carrier; laying down a layer of photoresist and patterning with a grid of copper via posts; plating copper into the grid; laminating with polymer dielectric; thinning and planarizing to expose ends of copper vias; removing the carrier, and machining chip sockets in the polymer dielectric.
17 . The method of claim 16 , wherein the carrier is a copper carrier that is removed by dissolving the copper.
18 . The method of claim 16 further comprising applying an etch resistant layer over the carrier prior to depositing the copper via posts.
19 . The method of claim 16 , wherein the etch resistant layer comprises nickel.
20 . The method of claim 16 , wherein the planarized polymer dielectric with exposed ends of copper vias posts is protected with an etch resistant material whilst copper carrier is etched away.
21 . The method of claim 20 wherein the etch resistant material is a photoresist.
22 . The method of claim 18 wherein a copper seed layer is electroplated over the nickel.
23 . The method of claim 18 wherein a copper seed layer is electroplated prior to depositing the nickel barrier layer.
24 . The method of claim 16 , wherein the grid is machined by one of punching out sockets leaving a framework or by CNC.
25 . A method of fabricating an array of chip sockets surrounded by an organic matrix framework comprising:
obtaining a sacrificial carrier; laying down a layer of photoresist and patterning with a grid of copper via posts and a chip socket array; plating copper into the grid and the array; laminating with polymer dielectric; thinning and planarizing to expose ends of copper vias and the array; shielding the ends of the copper vias posts; dissolving the array, and removing the carrier.
26 . The method of claim 25 wherein the via posts are elongated via posts and at least one chip socket is surrounded by an organic matrix frame with an embedded metallic structure comprise at least one elongated via post and at least one feature layer.
27 . The method of claim 25 wherein the elongated via post and feature layer comprises a continuous coil.
28 . The method of claim 25 wherein at least one socket is surrounded by an organic frame and a multilayer metal structure embedded in the organic frame and comprising a plurality of extended via post layers, such that each pair of adjacent via post layers are separated by a feature layer and the multilayer metal structure comprises a continuous coil.Join the waitlist — get patent alerts
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