Voltage polarity detection for dcm/ccm boundary detection in dc/dc converters

Abstract

There is described a circuit and a method of detecting a voltage polarity for the detection of a Continuous Conduction Mode to Discontinuous Conduction Mode boundary of a switched DC-DC converter. There is provided use of a dynamic current mirror to store in a first capacitor (C) a voltage representative of the conduction voltage (V DS(Φ1) ) of the power switch, at the end of a conduction cycle of said power switch. Also, an auto-zero comparator is used to charge the output voltage of the dynamic current mirror into a second capacitor (C 2 ), during the first phase of operation corresponding to a conduction cycle of the power switch, and to detect the polarity of the conduction voltage (V DS(t=TCLK )) of the power switch at the end of the first phase of operation of the DC-DC converter, by comparing the voltage stored in the second capacitor during the first phase of operation with the output voltage of the dynamic current mirror in a second phase of operation (Φ 2 ) corresponding to a non-conduction cycle of the power switch.

1 . A voltage polarity detection circuit adapted for the detection of a Continuous Conduction Mode to Discontinuous Conduction Mode boundary of a power switch in a switched DC/DC converter, said circuit comprising:
 an input for receiving an input voltage representative of the conduction voltage of the power switch;   an output for outputting a voltage polarity detection signal;   a dynamic current mirror having an input connected to the input of the circuit through a first capacitor, and an output, said dynamic current mirror being controlled to store a voltage representative of the input voltage in the first capacitor at the end of a conduction cycle of the power switch; and,   an auto-zero comparator having a first input connected to the output of the dynamic current mirror, a second input connected to a second capacitor, and an output connected to the output of the circuit, said auto-zero comparator being controlled to:
 charge the output voltage of the dynamic current mirror into the second capacitor, during a first phase of operation corresponding to the conduction cycle of the power switch; and, 
 detect the polarity of the input voltage at the end of the first phase of operation, by comparing the voltage stored in the second capacitor with the output voltage of the dynamic current mirror in a second phase of operation corresponding to a non-conduction cycle of the power switch. 
   
     
     
         2 . The circuit of  claim 1 , wherein the dynamic current mirror comprises:
 a main current source adapted to output a main constant current; and,   a single main MOS transistor whose drain is connected to the current source for receiving said constant current, whose source is connected to a first power supply, and whose control gate is connected:
 to input of the dynamic current mirror through the first capacitor and a first control switch; 
 to the first power supply through the first capacitor and a second control switch; and, 
 to its drain through a third control switch. 
   
     
     
         3 . The circuit of  claim 1 , wherein the auto-zero comparator comprises an Operational Amplifier whose non-inverting input is connected to the first input of the comparator, whose inverting input is connected to the first power supply through the second capacitor, and whose output is connected to the non-inverting input through a fourth control switch and to the output of the comparator. 
     
     
         4 . The circuit of  claim 1 , wherein the first, third and fourth control switches on one hand, and the second control switch, on the other hand, are driven by a first and a second one, respectively, of two complementary clock signals, such that the first, third and fourth control switches are closed and the second control switch in open in the first phase of operation, and that the first, third and fourth control switches are open and the second control switch is closed in the second phase of operation. 
     
     
         5 . The circuit of  claim 1 , wherein the dynamic current mirror further comprises a cascode stage having a first additional MOS transistor whose source is connected to the source of the main MOS transistor, whose drain is connected to an additional current source adapted to output an additional constant current, and whose control gate is connected to the drain of said main transistor, as well as a second additional MOS transistor whose source is connected to the drain of the main transistor, whose drain is connected to the main current source for receiving the main constant current, and whose control gate is connected to the drain of the first additional transistor. 
     
     
         6 . The circuit of  claim 4 , wherein the third control switch is implemented by a main transistor, the circuit further comprising a first and/or a second dummy transistors provided in the current path of said main transistor implementing the third control switch, on either side of said main transistor implementing the third control switch, respectively, namely on the drain side and on the source side of said main transistor, respectively, said first and/or second dummy transistors each being controlled by a clock signal which is complementary to the clock signal controlling said main transistor implementing the third control switch. 
     
     
         7 . The circuit of  claim 6 , wherein the first and/or second dummy transistors have a size 0.5×W and 1×L, as compared with the size W and L of said main transistor, respectively. 
     
     
         8 . The circuit of  claim 4 , wherein the fourth control switch is implemented by a main transistor, the circuit further comprising a dummy transistor provided in the current path of said main transistor implementing the fourth control switch, on the side of the second capacitor, said dummy transistor being controlled by a clock signal which is complementary to the clock signal controlling said main transistor implementing the fourth control switch. 
     
     
         9 . The circuit of  claim 4 , wherein the first control switch is implemented by a main transistor, the circuit further comprising a series and shunt switching arrangement associated to said main transistor implementing the first control switch, said series and shunt switching arrangement comprising, in addition to the serially connected main transistor implementing the first control switch, another serially connected transistor which is controlled by the same clock signal as said main transistor implementing the first control switch, and a parallel connected transistor controlled by a clock signal which is complementary to clock signal which controls said main transistor implementing the first control switch. 
     
     
         10 . The circuit of  claim 4 , wherein the two complementary clock signals are non-overlapping. 
     
     
         11 . The circuit of  claim 2 , further comprising a reference ground switching arrangement, so arranged that the first power supply is the power ground of the power stage of the DC/DC converter during the first phase of operation and is distinct from said power ground during the second phase of operation. 
     
     
         12 . The circuit of  claim 4 , wherein the circuit is powered during the first phase of operation, only until the voltage at the first input of the auto-zero comparator crosses the voltage at the second input of said auto-zero comparator, and is then turned off until the beginning of the next conduction cycle of the power switch. 
     
     
         13 . A method of detecting a voltage polarity for the detection of a Continuous Conduction Mode to Discontinuous Conduction Mode boundary of a power switch used in a switched DC-DC converter, comprising:
 using a dynamic current mirror to store in a first capacitor a voltage representative of the conduction voltage of the power switch, at the end of a conduction cycle of said power switch; and,   using an auto-zero comparator to:
 charge the output current of the dynamic current mirror into a second capacitor during a first phase of operation corresponding to the conduction cycle of the power switch; and, 
 detect the polarity of the conduction voltage of the power switch at the end of the first phase of operation, by comparing the voltage stored in the second capacitor during the first phase of operation with the output voltage of the dynamic current mirror in a second phase of operation corresponding to a non-conduction period of the power switch. 
   
     
     
         14 . A DC/DC converter comprising:
 a power stage having at least one power switch; and,   at least one voltage polarity detection circuit according to  claim 1 , for the detection of a Continuous Conduction Mode to Discontinuous Conduction Mode boundary of the power switch.   
     
     
         15 . The DC/DC converter of  claim 14 , wherein the power switch comprises a power Metal Oxyde Semiconductor, MOS, transistor and wherein the input voltage of the voltage polarity detection circuit is the drain-source voltage of said power MOS transistor. 
     
     
         16 . A mobile device comprising a DC/DC converter according to  claim 15 .