Semiconductor device and electronic device

Abstract

A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.

What is claimed is: 
     
         1 - 12 . (canceled) 
     
     
         13 . A semiconductor device comprising:
 a central processing unit;   a data bus; and   a communication controller coupled with the central processing unit via the data bus, which is configured to control communication with an interface IC,   the communication controller comprising:
 a clock input buffer configured to receive an external clock signal from the interface IC; 
 a data input buffer configured to receive input data from the interface IC; 
 an input circuit configured to receive the input data from the data input buffer and output the input data to the central processing unit via the data bus; 
 an output circuit configured to receive output data from the central processing unit via the data bus; 
 a data output buffer configured to receive the output data from the output circuit and output the output data to the interface IC; 
 a first PLL circuit coupled with the clock input buffer and the input circuit; 
 a first delay circuit coupled with the first PLL circuit; 
 a second PLL circuit coupled with the clock input buffer and the output circuit; and 
 a second delay circuit coupled with the second PLL circuit, 
   wherein the first delay circuit is configured to delay a first feedback signal outputted from the first PLL circuit to generate a first delay clock signal and output the first delay clock signal to the first PLL circuit,   wherein the first PLL circuit is configured to perform phase adjustment between the external clock signal and the first delay clock signal to generate a first internal clock signal,   wherein the input data is transferred from the input data buffer to the input circuit in accordance with the first internal clock signal,   wherein the second delay circuit is configured to delay a second feedback signal outputted from the second PLL circuit to generate a second delay clock signal and output the second delay clock signal to the second PLL circuit,   wherein the second PLL circuit is configured to perform phase adjustment between the external clock signal and the second delay clock signal to generate a second internal clock signal, and   wherein the output data is transferred from the output circuit to the output buffer in accordance with the second internal clock signal.   
     
     
         14 . The semiconductor device according to  claim 13 , wherein the first internal clock signal is outputted from the first PLL circuit based on a delay amount in the first delay circuit. 
     
     
         15 . The semiconductor device according to  claim 14 , wherein the input data satisfies a setup time and a hold time that are determined in advance. 
     
     
         16 . The semiconductor device according to  claim 13 , wherein the second internal clock signal is outputted from the second PLL circuit based on a delay amount in the second delay circuit. 
     
     
         17 . The semiconductor device according to  claim 16 , wherein the output data is outputted within a predetermined period of time after the external clock signal is inputted. 
     
     
         18 . The semiconductor device according to  claim 17 , wherein the delay amount in the second delay circuit is determined so that the output data to which the delay time is added in the output circuit is outputted within the predetermined period of time after the external clock signal is inputted. 
     
     
         19 . The semiconductor device according to  claim 13 , further comprising a module controller that controls the communication controller using a program. 
     
     
         20 . The semiconductor device according to  claim 13 , wherein the semiconductor device is an electronic device. 
     
     
         21 . The semiconductor device according to  claim 20 , wherein the electronic device is a car navigation system.