Same layer microelectronic circuit patterning using hybrid laser projection patterning (lpp) and semi-additive patterning (sap)

Abstract

In some embodiments, same layer microelectronic circuit patterning using hybrid laser projection patterning (LPP) and semi-additive patterning (SAP) is presented. In this regard, a method is introduced including patterning a first density region of a laminated substrate surface using LPP, patterning a second density region of the laminated substrate surface using SAP, and plating the first and second density regions of the laminated substrate surface, wherein features spanning the first and second density regions are directly coupled. Other embodiments are also disclosed and claimed.

1 . (canceled) 
     
     
         2 . A system comprising:
 a package substrate including a necking region and a main routing region, the main routing region contiguous with the necking region and extending outwardly from the necking region;   a die situated on the substrate, wherein the necking region includes an area of the substrate within a footprint of the die;   a plurality of first traces situated on the substrate in the necking region; and   a plurality of second traces situated on the substrate in the main routing region, each coupled to a respective first trace of the plurality of first traces.   
     
     
         3 . The system of  claim 2 , wherein a width of each of the first traces is less than a width of each of the second traces. 
     
     
         4 . The system of  claim 3 , wherein the width of each of the second traces is greater than fourteen micrometers. 
     
     
         5 . The system of  claim 4 , wherein the width of each of the first traces is about nine micrometers. 
     
     
         6 . The system of  claim 2 , wherein a spacing between traces of the first plurality of traces is less than a spacing between traces of the second plurality of traces. 
     
     
         7 . The system of  claim 6 , wherein the spacing between traces of the second plurality of traces is greater than about fourteen micrometers. 
     
     
         8 . The system of  claim 7 , wherein the spacing between traces of the first plurality of traces is about nine micrometers. 
     
     
         9 . The system of  claim 2 , wherein the first plurality of traces are situated within ablated regions of the substrate. 
     
     
         10 . The system of  claim 9 , wherein each of the second plurality of traces overlap with and electrically contact a first trace of the first plurality of traces in an outer portion of the necking region. 
     
     
         11 . The system of  claim 9 , wherein each of the second plurality of traces electrically contacts a first trace of the first plurality of traces and is co-planar with the first trace of the first plurality of traces. 
     
     
         12 . The system of  claim 11 , wherein each of the first plurality of traces is situated in a dielectric protrusion of the substrate that extends beyond a top surface of the main routing region of the substrate. 
     
     
         13 . The system of  claim 2 , wherein a routing density of the first plurality of traces is greater than a routing density of the second plurality of traces. 
     
     
         14 . A method comprising:
 patterning a first density region of a laminated substrate surface using laser projection patterning (LPP);   patterning a second density region of the laminated substrate surface using semi-additive patterning (SAP); and   plating the first and second density regions of the laminated substrate surface, wherein features spanning the first and second density regions are directly coupled.   
     
     
         15 . The method of  claim 14 , wherein the first density region comprises a necking region wherein I/O signals from an integrated circuit die escape. 
     
     
         16 . The method of  claim 14 , wherein the second density region comprises a lower density main routing region. 
     
     
         17 . The method of  claim 14 , wherein plating the first and second density regions comprises plating the first and second density regions in a same copper plating step. 
     
     
         18 . The method of  claim 14 , wherein plating the first and second density regions comprises plating the first and second density regions in discrete copper plating steps. 
     
     
         19 . The method of  claim 14 , wherein the first density region comprises features having a length of a few millimeters. 
     
     
         20 . A method comprising:
 ablating a necking region into a laminated substrate surface with laser projection patterning (LPP);   plating the necking region with copper;   patterning a main routing region on the laminated substrate surface and necking region with dry film resist (DFR);   plating the main routing region; and   removing the DFR.   
     
     
         21 . The method of  claim 8 , wherein the necking region is slightly larger than a die shadow, and wherein plating the necking region with copper comprises electrolytic copper plating to a thickness of between about 5 and about 20 micrometers.