Highly compact non-volatile memory and method thereof

Abstract

A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.

What is claimed is: 
     
         1 . A method of reading or writing an array of non-volatile memory cells, comprising:
 providing a set of read/write circuits;   coupling said set of read/write circuits to a segment of a row of memory cells in the array in parallel, the memory cells in the segment of the row being adjacent to each other; and   operating said set of read/write circuits to read or write on said contiguous segment of a row of memory cells in the array in parallel.   
     
     
         2 . The method as in  claim 1 , wherein said segment of a row extends to the entire row. 
     
     
         3 . The method as in any one of  claim 1 , wherein said array of non-volatile memory cells is organized into erasable blocks of EEPROM cells. 
     
     
         4 . The method as in any one of  claim 1 , wherein said array of non-volatile memory cells is organized into erasable blocks of EEPROM cells. 
     
     
         5 . The method as in any one of  claim 1 , wherein said array of the non-volatile memory cells is of the NAND type. 
     
     
         6 . The method as in any one of  claim 1 , wherein said array of the non-volatile memory cells is of the NAND type. 
     
     
         7 . The method as in any one of  claim 1 , wherein said plurality of non-volatile memory cells is constituted from NROM cells. 
     
     
         8 . The method as in any one of  claim 1 , wherein said plurality of non-volatile memory cells is constituted from NROM cells. 
     
     
         9 . The method as in any one of  claim 1 , wherein each memory cell stores one bit of data. 
     
     
         10 . The method as in any one of  claim 1 , wherein each memory cell stores one bit of data. 
     
     
         11 . The method as in any one of  claim 1 , wherein each memory cell stores more than one bit of data. 
     
     
         12 . The method as in any one of  claim 2 , wherein each memory cell stores more than one bit of data.