Semiconductor memory device with power interruption detection and reset circuit

Abstract

A control logic unit generates a control signal which is activated while a power supply normally operates. A charge circuit is connected to a first node on a voltage control line supplied with a voltage generated by a voltage generation circuit, so that its capacitive element is charged with electric charge. A first discharge circuit is connected to a charge storage node of the charge circuit and discharges the stored electric charge when the control signal is activated. A second discharge circuit discharges the first node when the charge storage node has a potential exceeding a predetermined potential.

1 . A semiconductor device comprising:
 a plurality of memory cells each storing data depending on a change in level of a threshold voltage;   a voltage generation circuit generating a voltage to be applied to said memory cell;   a control logic unit generating a control signal activated while a power supply voltage is normally supplied;   a charge circuit coupled to a first node on a voltage control line supplied with the voltage generated by said voltage generation circuit, said charge circuit including a second node and a capacitive element coupled to said second node;   a first discharge circuit coupled to said second node, and coupling said second node to a ground potential when said control signal is activated; and   a second discharge circuit coupling said first node to said ground potential when a voltage of said second node exceeds a threshold voltage value of said second discharge circuit.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein said control logic unit generates said control signal periodically activated to indicate that a power supply voltage is normally supplied. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein said control logic unit generates said control signal kept in an activated state to indicate that a power supply voltage is normally supplied. 
     
     
         4 . The semiconductor device according to  claim 3 , wherein
 said control logic unit includes:
 a plurality of flip-flops; and 
 a logic circuit which outputs, as said control signal, a logical product of respective outputs of said plurality of flip-flops, and 
   a transistor in at least one of said plurality of flip-flops has a size different from a size of a transistor in other flip-flops.   
     
     
         5 . The semiconductor device according to  claim 1 , wherein said first discharge circuit includes a transistor disposed between said second node and the ground potential and having a control electrode receiving said control signal. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein said second discharge circuit includes a transistor disposed between said first node and the ground and having a control electrode connected to said second node. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein said charge circuit includes:
 a load element disposed between said first node and said second node; and   said capacitive element disposed between said second node and the ground potential.   
     
     
         8 . The semiconductor device according to  claim 1 , wherein
 said semiconductor device is a microcomputer further comprising a system controller, and   said semiconductor device further comprises a reset request circuit activating, when the voltage of said second node exceeds said threshold voltage value of said second discharge circuit, a notification signal for requesting said system controller to reset the microcomputer including a nonvolatile semiconductor memory.   
     
     
         9 . The semiconductor device according to  claim 1 , wherein the voltage generated by said voltage generation circuit and supplied to said voltage control line is a memory gate voltage to be applied to a memory gate of said memory cell. 
     
     
         10 . A semiconductor device comprising:
 a plurality of memory cells each storing data depending on a change in level of a threshold voltage;   a voltage generation circuit generating a voltage to be applied to said memory cell;   a control logic unit generating a control signal periodically activated to indicate that a power supply voltage is normally supplied; and   a circuit receiving said control signal, detecting short interruption of said power supply voltage from said control signal failing to be regularly activated, and accordingly discharging a voltage of a first node on a voltage control line supplied with the voltage generated by said voltage generation circuit.