Level shift circuit

Abstract

A level shift circuit includes a first pair of transistors of the first conductive type (M 1 , M 4 ) with sources coupled to a pair of input nodes (in, inB) and gates coupled to the first power supply (GND) in common; a second pair of transistors of the second conductive type (M 2 , M 5 ) with drains coupled to the drains of the first pair of the transistors and the gates coupled to the first power supply in common; a third pair of transistors of the second conductive type (M 3 , M 6 ) with cross-coupled gates and drains coupled to the sources of the second pair of transistors and the sources coupled to the second power supply (V 2 ) in common; and a pair of capacitative elements (C 1 , C 2 ) with one ends coupled to the pair of input nodes and the other ends coupled to the drains of the third pair of transistors.

What is claimed is: 
     
         1 . A level shift circuit comprising:
 a first pair of transistors of a first conductive type, sources of the first pair of transistors being coupled to a pair of input nodes and gates of the first pair of transistors being coupled to a first power supply in common;   a second pair of transistors of a second conductive type, drains of the second pair of transistors being coupled to drains of the first pair of transistors and gates of the second pair of transistors being coupled to the first power supply in common;   a third pair of transistors of the second conductive type, drains of the third pair of transistors being coupled to sources of the second pair of transistors and gates and drains of the third pair of transistors being cross-coupled to each other;   a pair of capacitative elements, one ends of the elements being coupled to the pair of input nodes while other ends of the elements being coupled to the drains of the third pair of transistors; and   a resister element, one end of the element being coupled to sources of the third pair of transistors in common while the other end of the element being coupled to a second power supply.   
     
     
         2 . A level shift circuit comprising:
 a first pair of transistors of a first conductive type, sources of the first pair of transistors being coupled to a pair of input nodes and gates of the first pair of transistors being coupled to a first power supply in common;   a second pair of transistors of a second conductive type, drains of the second pair of transistors being coupled to drains of the first pair of transistors and gates of the second pair of transistors being coupled to the first power supply in common;   a third pair of transistors of the second conductive type, drains of the third pair of transistors being coupled to sources of the second pair of transistors and gates and drains of the third pair of transistors being cross-coupled to each other;   a pair of capacitative elements, one ends of the elements being coupled to the pair of input nodes while other ends of the elements being coupled to the drains of the third pair of transistors; and   a third transistor of the second conductive type, a drain of the third transistor being coupled to sources of the third pair of transistors in common, and a source of the third transistor being coupled to a second power supply.   
     
     
         3 . The level shift circuit according to  claim 1 , further comprising:
 a first transistor of the second conductive type, a gate of the transistor being coupled to a drain of one of the first pair of transistors and a source of the transistor being coupled to a source of one of the second pair of transistors while a drain of the transistor being coupled to the first power supply.   
     
     
         4 . A port selection circuit comprising:
 a switch circuit; and   a level shift circuit according to  claim 1  in which said pair of input nodes is driven between a third power supply potential and said first power supply potential,   wherein a control terminal of said switch circuit is driven to said third or second power supply potential by means of said level shift circuit.   
     
     
         5 . A port selection circuit comprising:
 a switch circuit; and   a level shift circuit according to  claim 2  in which said pair of input nodes is driven between a third power supply potential and said first power supply potential,   wherein a control terminal of said switch circuit is driven to said third or second power supply potential by means of said level shift circuit.