High-performance cache system and method

Abstract

A digital system including a processor core and a cache control unit is disclosed. The processor core is capable of being coupled to a first memory containing data and a second memory with a faster speed than the first memory, and is configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register. The cache control unit is configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data. Further, the cache control unit is further configured to examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information and to create a track corresponding to the segment of instructions based on the extracted instruction information. The cache control unit is also configured to fill the data from the first memory to the second memory based on the track corresponding to the segment of instructions after execution of an instruction last updating the base register used by the at least one instruction accessing the data.

What is claimed is: 
     
         1 . A digital system, comprising:
 a processor core capable of being coupled to a first memory containing data and a second memory with a faster speed than the first memory, and configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register; and   a cache control unit configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data,   wherein the cache control unit is further configured to:
 examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information; 
 create a track corresponding to the segment of instructions based on the extracted instruction information; and 
 fill the data from the first memory to the second memory based on the track corresponding to the segment of instructions after execution of an instruction last updating the base register used by the at least one instruction accessing the data.