Semiconductor memory device

Abstract

A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.

1 - 14 . (canceled) 
     
     
         15 . A semiconductor memory device comprising:
 a memory cell array region having a plurality of normal column lines and a plurality of repair column lines;   a plurality of normal column line selection units suitable for selecting the plurality of normal column lines, respectively, in response to a local column address;   a plurality of repair column line selection units suitable for selecting the plurality of repair column lines, respectively, in place of normal column line selection units corresponding to fail information of the local column address among the plurality of normal column line selection units;   a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal column line selection units corresponding to the fail information, and enabling normal column line selection units unrelated to the fail information; and   an address determination unit suitable for controlling the plurality of repair column line selection units based on the fail information programmed in the fuse array.   
     
     
         16 . The semiconductor memory device of  claim 15 , wherein the fuse driving unit includes a control signal generator suitable for generating a control signal for selectively controlling whether to enable and disable the plurality of normal column line selection units based on the fail information programmed in the fuse array. 
     
     
         17 . The semiconductor memory device of  claim 16 , wherein the fuse driving unit further includes a rupture operation controller suitable for receiving a rupture signal and performing a rupture operation on the fuse array. 
     
     
         18 . The semiconductor memory device of  claim 15 , wherein the address determination unit includes:
 an address latch suitable for receiving the fail information programmed in the fuse array and latching the fail information during a boot-up operation;   an address comparator suitable for comparing the latched fail information with the local column address; and   a select signal generator suitable for generating a repair column line select signal for controlling the plurality of repair column line selection units to select the plurality of repair column lines when the local column address coincides with the fail information.   
     
     
         19 . The semiconductor memory device of  claim 15 , further comprising:
 a strobe signal generation unit suitable for generating a strobe signal for selecting whether to enable and disable the plurality of normal column line selection units and the plurality of repair column line selection units.