Method of forming a cmos structure having gate insulation films of different thicknesses

Abstract

The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

1 . A method of manufacturing a semiconductor device for fabrication of a plurality of metal oxide semiconductor (MOS) transistors having gate insulation films different in thickness on the same silicon substrate, wherein the gate insulation films of different thicknesses are formed separately. 
     
     
         2 . The method of manufacturing a semiconductor device of  claim 1 , wherein a gate insulation film thickness of a first MOS transistor is 3.5 nm or less. 
     
     
         3 . The method of manufacturing a semiconductor device of  claim 1 , wherein a gate insulation film thickness of a second MOS transistor is 5.0 nm or less. 
     
     
         4 . The method of manufacturing a semiconductor device of  claim 3 , wherein a gate insulation film thickness of the second MOS transistor is 10.0 nm or less. 
     
     
         5 . The method of manufacturing a semiconductor device of  claim 1 , wherein the plurality of MOS transistors comprises a first and a second MOS transistors, wherein a gate length of the second MOS transistor is longer than the gate length of the first MOS transistor. 
     
     
         6 . The method of manufacturing a semiconductor device of  claim 1 , wherein the plurality of MOS transistors comprises a first, a second, and a third MOS transistors, wherein the third MOS transistor has a drain connected to a drain of the first MOS transistor and a gate insulation film thickness thinner than that of the second MOS transistor; and a power supply line connected to a source of the third MOS transistor, wherein the first and second MOS transistors provide N-channel type; and the third MOS transistor has a different conductivity type with the first and second MOS transistors. 
     
     
         7 . The method of manufacturing a semiconductor device of  claim 6 , wherein the first and third MOS transistors are short-circuited. 
     
     
         8 . A method of manufacturing a semiconductor device for fabrication of a plurality of MOS transistors having gate insulation films different in thickness on the same silicon substrate, wherein a gate insulation film less in thickness is formed prior to formation of a gate insulation film greater in thickness. 
     
     
         9 . The method of manufacturing a semiconductor device of  claim 8 , wherein the plurality of MOS transistors comprises a first, a second, and a third MOS transistors. 
     
     
         10 . The method of manufacturing a semiconductor device of  claim 9 , wherein a gate insulation film of the first MOS transistor is less than that of the second and third MOS transistors. 
     
     
         11 . The method of manufacturing a semiconductor device of  claim 9 , wherein a gate width of the third MOS transistor is larger than a gate width of the first transistor. 
     
     
         12 . The method of manufacturing a semiconductor device of  claim 9 , wherein the second MOS transistor and the third MOS transistor are controlled by the same control signal. 
     
     
         13 . The method of manufacturing a semiconductor device of  claim 9 , wherein a gate length of the second MOS transistor is longer than a gate length of the first MOS transistor, and wherein a gate length of the third MOS transistor is longer than a gate length of the first MOS transistor. 
     
     
         14 . A method of manufacturing a semiconductor device comprising on the same silicon substrate a plurality of MOS transistors each having a lamination of a gate insulation film and a gate electrode, said plurality of MOS transistors including a first MOS transistor and a second MOS transistor different from each other in thickness of the gate insulation film, said method comprising the steps of:
 forming the gate insulation film of said first MOS transistor to a thickness less than that of said second MOS transistor;   forming the gate insulation film and the gate electrode of said second. MOS transistor; and   forming thereafter the gate insulation film and the gate electrode of said first MOS transistor.   
     
     
         15 . The method of manufacturing a semiconductor device of  claim 14 , wherein a gate insulation film thickness of the first MOS transistor is 3.5 nm or less. 
     
     
         16 . The method of manufacturing a semiconductor device of  claim 14 , wherein a gate insulation film thickness of the second MOS transistor is 5.0 nm or less. 
     
     
         17 . The method of manufacturing a semiconductor device of  claim 16 , wherein a gate insulation film thickness of the second MOS transistor is 10.0 nm or less. 
     
     
         18 . The method of manufacturing a semiconductor device of  claim 14 , wherein a gate length of the second MOS transistor is longer than the gate length of the first MOS transistor. 
     
     
         19 . The method of manufacturing a semiconductor device of  claim 14 , wherein the third MOS transistor has a drain connected to a drain of the first MOS transistor and a gate insulation film thickness thinner than that of the second MOS transistor; and a power supply line connected to a source of the third MOS transistor, wherein the first and second MOS transistors provide N-channel type; and the third MOS transistor has a different conductivity type with the first and second MOS transistors. 
     
     
         20 . The method of manufacturing a semiconductor device of  claim 14 , wherein a gate width of the third MOS transistor is larger than a gate width of the first transistor.