Double-sided vertical semiconductor device with thinned substrate

Abstract

A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

1 . A semiconductor device comprising:
 a semiconductor layer having a first surface, a second surface, a background doped region doped to a first conductivity type, and an etched portion exposing a third surface; the semiconductor layer comprising:
 a first doped region, adjacent to the second surface, of a second conductivity type opposite the first conductivity type, 
 a second doped region of the first conductivity type, the second doped region being adjacent to the second surface and formed inside the first doped region, and 
 a diffused region of the second conductivity type extending from the first doped region to the third surface; 
   a first electrical contact to the second doped region at the second surface; and   a physical contact to the diffused region at the third surface, the physical contact creating a second electrical contact to the first doped region at the third surface.   
     
     
         2 . The semiconductor device of  claim 1 , wherein:
 the semiconductor layer further comprises a third doped region adjacent to the third surface, the third doped region being separated from the first surface and separated from the first doped region; and   the semiconductor device further comprises a third electrical contact to the third doped region at the third surface.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the third doped region has the first conductivity type. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the background doped region is doped uniformly to a first doping concentration, and wherein the third doped region has a peak doping concentration greater than 10 times the first doping concentration. 
     
     
         5 . The semiconductor device of  claim 2 , wherein the third doped region has the second conductivity type. 
     
     
         6 . The semiconductor device of  claim 2 , wherein the third doped region has a doping concentration greater than 10 18  cm −3 . 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first electrical contact electrically connects the first doped region to the second doped region. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising an interconnect layer coupled to the second surface of the semiconductor layer, wherein the first electrical contact extends from the second surface of the semiconductor layer through the interconnect layer. 
     
     
         9 . The semiconductor device of  claim 8 , further comprising a handle layer coupled to the interconnect layer. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the semiconductor layer comprises:
 an insulator layer having a first surface, a second surface, and an etched portion;   a semiconductor-on-insulator layer having a first surface and a second surface, the first surface contacting the first surface of the insulator layer, the second surface corresponding to the second surface of the semiconductor layer, and a portion of the first surface exposed by the etched portion of the insulator layer corresponding to the third surface of the semiconductor layer; and   a substrate layer having a first surface, a second surface, and an etched portion, the second surface contacting the second surface of the insulator layer, the first surface corresponding to the first surface of the semiconductor layer, and the etched portion of the substrate layer enclosing or coincident with the etched portion of the insulator layer.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the etched portion of the substrate layer comprises the entire substrate layer. 
     
     
         12 . The semiconductor device of  claim 1 , wherein the first electrical contact comprises a refractory metal. 
     
     
         13 . The semiconductor device of  claim 15 , wherein the semiconductor layer comprises:
 an insulator layer having a front surface, a back surface, and an etched portion;   a semiconductor-on-insulator (SOI) layer having a front surface and a back surface, wherein the front surface of the SOI layer corresponds to the front surface of the semiconductor layer, and wherein the etched portion of the insulator layer exposes at least a portion of the back surface of the SOI layer, said exposed portion corresponding to the second back surface of the semiconductor layer; and   a substrate layer having a front surface, a back surface, and an etched portion, wherein the front surface of the substrate layer contacts the back surface of the insulator layer, the back surface of the substrate layer corresponds to the first back surface of the semiconductor layer, and the etched portion of the substrate layer encloses or is coincident with the etched portion of the insulator layer.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the etched portion of the substrate layer comprises the entire substrate layer. 
     
     
         15 . A semiconductor device comprising:
 a semiconductor layer having a front surface, a first back surface, and a background doped region doped to a first conductivity type, wherein at least a portion of the first back surface is etched to expose a second back surface, and wherein the semiconductor layer comprises:
 a first doped region adjacent to the front surface, the first doped region having a second conductivity type opposite the first conductivity type; 
 a second doped region adjacent to the front surface and contained within the first doped region, the second doped region having the first conductivity type; and 
 a diffused region of the second conductivity type extending from the first doped region to the second back surface, the diffused region having the second conductivity type; 
   a front-side contact to the second doped region at the front surface; and   a back-side contact to the diffused region at the second back surface.   
     
     
         16 . The semiconductor device of  claim 15 , wherein:
 the semiconductor layer further comprises a third doped region adjacent to the second back surface, the third doped region being separated from the front surface and the first doped region; and   the semiconductor device further comprises a second back-side contact to the third doped region at the second back surface.   
     
     
         17 . The semiconductor device of  claim 16 , wherein the third doped region has the first conductivity type. 
     
     
         18 . The semiconductor device of  claim 16 , wherein the third doped region has the second conductivity type. 
     
     
         19 . The semiconductor device of  claim 15 , wherein the front-side contact electrically connects the first doped region to the second doped region. 
     
     
         20 . The semiconductor device of  claim 15 , further comprising an interconnect layer coupled to the front surface of the semiconductor layer, wherein the front-side contact extends from the front surface of the semiconductor layer through the interconnect layer. 
     
     
         21 . The semiconductor device of  claim 1 , wherein:
 the first electrical contact biases the second doped region and does not bias the first doped region or the diffused region; and   the second electrical contact biases the diffused region and does not bias the second doped region.   
     
     
         22 . The semiconductor device of  claim 21 , further comprising:
 the semiconductor layer is a portion of a bulk semiconductor wafer.   
     
     
         23 . The semiconductor device of  claim 15 , wherein:
 the front-side contact biases the second doped region and does not bias the first doped region or the diffused region; and   the back-side contact biases the diffused region and does not bias the second doped region.   
     
     
         24 . The semiconductor device of  claim 23 , wherein:
 the semiconductor layer is a portion of a bulk semiconductor wafer.