Soft Error Protection For Content Addressable Memory

Abstract

In one embodiment of the invention, a method for protecting a content addressable memory is disclosed. The method includes storing a marker bit associated with each data block stored in a random access memory (RAM), states of the marker bit representing whether the data block was recently read from the RAM or recently written into the RAM; receiving a client address pointing to a starting address of a data block stored in the RAM; comparing the client address against one or more addresses stored in a content addressable memory (CAM) to determine a hit indicating the client address was stored in the CAM or a miss indicating the client address was not stored in the CAM; and in response to a miss, the method further includes checking a state of the marker bit associated with the data block pointed to by the client address.

1 . A method comprising:
 storing a bit that indicates a data block was transferred between a cache and a random access memory (RAM);   receiving an address of the data block;   comparing the received address against one or more addresses stored in a content addressable memory (CAM) to determine a hit indicating the received address was stored in the CAM or a miss indicating the received address was not stored in the CAM; and   checking the bit in response to a miss.   
     
     
         2 . The method of  claim 1 , wherein the method comprises:
 indicating that the miss was a false miss if it is determined, in response to the checking, that the bit indicates that the data block was recently read from the RAM into the cache.   
     
     
         3 . The method of  claim 2 , wherein the method comprises:
 scrubbing the one or more addresses stored in the CAM if a false miss is indicated.   
     
     
         4 . The method of  claim 1 , wherein the method comprises:
 reading the data block, associated with the address, from the RAM into the cache if it is determined that the bit indicates that the data block was recently written into the RAM.   
     
     
         5 . The method of  claim 4 , wherein the comprises:
 storing the data block read out from the RAM into the cache in response to the miss; and   storing the received address into the CAM in response to the miss.   
     
     
         6 . The method of  claim 1 , wherein the method comprises:
 pointing to a starting address location in the cache for the data block in response to the hit.   
     
     
         7 . The method of  claim 1 , wherein the method comprises:
 in response to a hit,   generating a computed hash value from the received address in response to a hit,   reading a stored hash value out of a hash table corresponding to a tag generated by the CAM; and   comparing the stored hash value against the computed hash value; and   if the stored hash value does not match the computed hash value then the hit is a false hit.   
     
     
         8 . The method of  claim 7 , wherein the method comprises:
 in response to the false hit, scrubbing the address stored in the CAM associated with the tag of the false hit.   
     
     
         9 . A system comprising:
 a cache;   a memory device;   a content addressable memory (CAM) operable to store address entries; and   a controller operable to compare received address with the stored address entries and to generate a miss signal if no stored address entry matches the received address, the controller being coupled to the CAM and the memory device, the controller being operable to generate a first state of a bit associated with each data block written from the cache into the memory device, the controller being operable to update the state to a second state opposite the first state for each bit associated with each data block read out of the memory device into the cache;   wherein in response to the miss signal, the controller is operable to check the state of the bit associated with the data block addressable by the received address.   
     
     
         10 . The system of  claim 9 , wherein
 in response to the check of the state of the bit, the controller detects an unexpected state and generates an error signal that is coupled to the CAM.   
     
     
         11 . The system of  claim 10 , wherein in response to the error signal, the CAM scrubs one or more address entries. 
     
     
         12 . (canceled) 
     
     
         13 . (canceled) 
     
     
         14 . The system of  claim 12 , wherein
 if a stored address entry matches the received address into the memory device, the CAM generates a hit signal and a tag pointer into the cache where one or more lines of data may be read out from or written into the cache.   
     
     
         15 . The system of  claim 12 , further comprising:
 a microcontroller coupled to the cache controller and the CAM, the microcontroller to receive the miss signal and the received address from the cache controller, the microcontroller including firmware to cause the CAM to scrub at least one memory line therein in response to the miss signal and the received address.   
     
     
         16 . The system of  claim 9 , wherein the controller includes:
 an error correction code and marker (ECC/marker) generator coupled between the cache and the memory device, the ECC/marker generator to receive one or more data blocks for writing into the memory device, generate and append an error correction code (ECC) and a marker bit to each data block, the ECC/marker generator to couple each data block with appended ECC and marker bit into the memory device; and   an error correction code and marker (ECC/marker) checker coupled between the cache and the memory device, the ECC/marker checker to receive each data block with appended ECC and marker bit read out from the memory device in response to a received address, the ECC/marker checker further to check for errors in the block of data in response to the error correction code (ECC) and to check a state of the marker bit against an expected state of the marker bit to detect a false miss generated by the CAM and generate an error signal.   
     
     
         17 . The system of  claim 16 , further comprising:
 a microcontroller coupled to the ECC/marker checker and the CAM, the microcontroller to receive the error signal and the received address, the microcontroller to cause the CAM to scrub at least one memory line therein in response to the error signal and the received address.   
     
     
         18 . A cache memory controller comprising:
 a write buffer to store one or more blocks of data;   a marker generator coupled to the write buffer to receive the one or more blocks of data, the marker generator to generate and append a marker bit to each block of data received from the write buffer;   an interface controller coupled to the marker generator to receive each block of data with the appended marker bit, the interface controller for writing and reading blocks of data with the appended marker bit into and out of a memory device; and   a marker checker coupled to the interface controller to receive a block of data with its respective appended marker bit read out from the memory device associated with a received address, the marker checker to check a state of the marker bit against an expected state of the marker bit to detect a false miss generated by a content addressable memory.   
     
     
         19 . The cache memory controller of  claim 18 , wherein
 the expected state of the marker bit indicating a false cache miss is one indicating that the block of data was previously read out of the memory device into a cache.   
     
     
         20 . The cache memory controller of  claim 19 , wherein the state of the marker bit indicating a true cache miss is one indicating that the block of data was not previously read out of the memory device and into the cache. 
     
     
         21 . The cache memory controller of  claim 19 , wherein in response to detecting a false cache miss, the marker checker to-signals to scrub at least one entry in the content addressable memory associated with the received address generating the false cache miss. 
     
     
         22 . The cache memory controller of  claim 18 , further comprising:
 a read buffer coupled to the marker checker to receive one or more blocks of data stripped of their respective marker bit, the read buffer to store the one or more blocks of data received from the marker checker; and   a cache interface controller coupled to the read buffer and the write buffer, the cache interface controller to receive the one or more blocks of data from the read buffer and store them in a cache, the cache interface controller to further read one or more blocks of data from the cache and couple them into the write buffer.