Semiconductor integrated circuit device

Abstract

The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

What is claimed is: 
     
         1 . A semiconductor integrated circuit device comprising:
 a plurality of memory cells arranged along a first direction, each of the plurality of memory cells including   first and second storage nodes,   a first inverter, an input of which is connected to the first storage node and an output of which is connected to the second storage node, including a first p-channel transistor and a first n-channel transistor,   a second inverter, an input of which is connected to the second storage node and an output of which is connected to the first storage node, including a second p-channel transistor and a second n-channel transistor,   a third n-channel transistor connected to the first storage node,   a fourth n-channel transistor connected to the second storage node, and   a gate electrode of the fourth n-channel transistor being connected to a gate electrode of the third transistor;   a first bit line connected to the third n-channel transistor of each of the plurality of memory cells;   a second bit line connected to the fourth n-channel transistors of the plurality of memory cells;   a memory cell power supply line being connected to source electrodes of the first and second p-channel transistors of each of the plurality of memory cells;   a power supply line that supplies a power voltage; and   a power transistor connected to the memory cell power supply line, the power transistor making an electrical pass between the power supply line and the memory cell power supply line,   wherein the plurality of memory cells has a first part, a second part and a third part,   wherein the first n-channel transistor and the fourth n-channel transistor are located in the first part,   wherein the first p-channel transistor and the second transistor are located in the second part,   wherein the second n-channel transistor and the third n-channel transistor are located in the third part.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the first part, the second part and the third part are arranged in order of the first part, the second part and the third part along a second direction,   wherein the first part and third part are p-well regions, and wherein the second part is n-well region.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein the power transistor have a gate electrode receiving a control signal for tuning on and off the power transistor.