Packaging substrate, method for manufacturing same, and chip packaging structure having same

Abstract

A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts is larger than that of each of the first conductive posts. A manufacturing method thereof is also provided.

What is claimed is: 
     
         1 . A packaging substrate comprising:
 a circuit board comprising a first base and a first conductive pattern layer formed on a first surface of the first base;   a plurality of first conductive posts extending from and electrically connected to the first conductive pattern layer; and   a plurality of second conductive posts extending from and electrically connected to the first conductive pattern layer, the height of each of the second conductive posts being larger than that of each of the first conductive posts.   
     
     
         2 . The packaging substrate of  claim 1 , wherein a solder cap is formed on a top end of each of the first conductive posts. 
     
     
         3 . The packaging substrate of  claim 1 , wherein a protective layer is formed on a top end of each of the second conductive posts, and the protective layer is gold plating over nickel. 
     
     
         4 . The packaging substrate of  claim 1 , wherein the circuit board further comprises a first solder mask covering part of the first surface exposed to the first conductive pattern layer and part of the first conductive pattern layer, the first solder mask defines a plurality of first openings corresponding to the first conductive posts and a plurality of second openings corresponding to the second conductive posts, the first conductive posts are located in the respective first openings, and the second conductive posts are located in the respective second openings. 
     
     
         5 . The packaging substrate of  claim 4 , wherein the circuit board further comprises a second conductive pattern layer formed on an opposing second surface of the first base and a second solder mask, the second solder mask defines a plurality of third openings, part of the second conductive pattern layer is exposed to the third openings. 
     
     
         6 . The packaging substrate of  claim 5 , wherein a protective layer is formed on the part of the second conductive pattern layer exposed to the third openings. 
     
     
         7 . The packaging substrate of  claim 1 , wherein the first conductive posts are located at a central portion of the first conductive pattern layer, and the second conductive posts surround the first conductive posts. 
     
     
         8 . A chip packaging structure comprising:
 a first chip packaging body comprising a packaging substrate and a first chip, the packaging substrate comprising:
 a circuit board comprising a first base and a first conductive pattern layer formed on a first surface of the first base; 
 a plurality of first conductive posts extending from and electrically connected to the first conductive pattern layer; and 
 a plurality of second conductive posts extending from and electrically connected to the first conductive pattern layer, the height of each of the second conductive posts being larger than that of each of the first conductive posts; 
   the first chip comprising a plurality of first electrode pads corresponding to the first conductive posts, the first electrode pads mechanically and electrically connected to the respective first conductive posts through first solder balls; and   a second chip packaging body comprising a connecting substrate and a second chip packaged on the connecting substrate, the connecting substrate comprising a plurality of first contact pads corresponding to the second conductive posts, and the first contact pads mechanically and electrically connected to the respective second conductive posts through second solder balls.   
     
     
         9 . The chip packaging structure of  claim 8 , wherein a sum of the height of each of the first conductive posts and the thickness of the first chip is equal to the height of each of the second conductive posts. 
     
     
         10 . The chip packaging structure of  claim 9 , wherein a solder cap is formed on a top end of each of the first conductive posts. 
     
     
         11 . The chip packaging structure of  claim 9 , wherein a protective layer is formed on a top end of each of the second conductive posts, and the protective layer is gold plating over nickel. 
     
     
         12 . The chip packaging structure of  claim 9 , wherein the circuit board further comprises a first solder mask covering part of the first surface exposed to the first conductive pattern layer and part of the first conductive pattern layer, the first solder mask defines a plurality of first openings corresponding to the first conductive posts and a plurality of second openings corresponding to the second conductive posts, the first conductive posts are located in the respective first openings, and the second conductive posts are located in the respective second openings. 
     
     
         13 . The chip packaging structure of  claim 12 , wherein the circuit board further comprises a second conductive pattern layer formed on an opposing second surface of the first base and a second solder mask, the second solder mask defines a plurality of third openings, part of the second conductive pattern layer is exposed to the third openings. 
     
     
         14 . The chip packaging structure of  claim 13 , wherein a protective layer is formed on the part of the second conductive pattern layer exposed to the third openings. 
     
     
         15 . The chip packaging structure of  claim 9 , wherein the first conductive posts are located at a central portion of the first conductive pattern layer, and the second conductive posts surround the first conductive posts.