Three dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns.

What is claimed is: 
     
         1 . A three-dimensional semiconductor memory device, comprising:
 a stacked structure including a plurality of conductive patterns vertically stacked on a substrate;   a selection structure including a plurality of selection conductive patterns stacked on the stacked structure;   a channel structure penetrating the selection structure and the stacked structure to connect to the substrate;   an upper interconnection line crossing the selection structure; and   a conductive pad disposed on the channel structure to electrically connect the upper interconnection line to the channel structure,   wherein a bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the plurality of selection conductive patterns.   
     
     
         2 . The device of  claim 1 , wherein the bottom surface of the conductive pad is positioned between top surfaces of two adjacent selection conductive patterns in a vertical direction. 
     
     
         3 . The device of  claim 1 , wherein the bottom surface of the conductive pad is positioned between top and bottom surfaces of the uppermost selection conductive pattern. 
     
     
         4 . The device of  claim 1 , wherein the bottom surface of the conductive pad is positioned below a bottom surface of the uppermost selection conductive pattern. 
     
     
         5 . The device of  claim 1 , wherein a thickness of the conductive pad is greater than that of the uppermost selection conductive pattern. 
     
     
         6 . The device of  claim 1 , wherein the conductive pad has impurities of a first conductivity type, and the channel structure comprises a channel impurity region having impurities of a second conductivity type and positioned adjacent to at least one of the plurality of selection conductive patterns,
 wherein bottom surfaces of the channel impurity region and the conductive pad are positioned at different vertical levels.   
     
     
         7 . The device of  claim 1 , wherein the plurality of selection conductive patterns is electrically connected to each other to be in an equipotential state. 
     
     
         8 . The device of  claim 1 , wherein the selection structure comprises a first selection conductive pattern provided at a top level thereof and at least two second selection conductive patterns provided between the first selection conductive pattern and the stacked structure, and
 the first selection conductive pattern is electrically separated from the second selection conductive patterns.   
     
     
         9 . The device of  claim 1 , further comprising:
 a vertical insulating layer vertically extending from a region between the channel structure and the stacked structure to a region between the channel structure and the selection structure; and   a horizontal insulating layer provided between the vertical insulating layer and the channel structure and extended to cover top and bottom surfaces of the selection conductive patterns and the conductive patterns.   
     
     
         10 . The device of  claim 1 , wherein the vertical insulating layer vertically extends from a region between the channel structure and the selection structure to cover a sidewall of the conductive pad. 
     
     
         11 . The device of  claim 1 , wherein at least one of the plurality of selection conductive patterns has substantially the same thickness as that of at least one of the plurality of conductive patterns. 
     
     
         12 . A three-dimensional semiconductor memory device, comprising:
 a first selection structure extending along a first direction and including a plurality of first selection conductive patterns vertically stacked on a substrate;   a second selection structure adjacent to the first selection structure and including a plurality of second selection conductive patterns vertically stacked on the substrate;   first and second channel structures penetrating the first and second selection structures, respectively;   an upper interconnection line crossing the first and second selection structures; and   first and second conductive pads provided on the first and second channel structures, respectively, to electrically connect the upper interconnection line to the first and second channel structures,   wherein bottom surfaces of the first and second conductive pads are positioned below top surfaces of the uppermost first and second selection conductive patterns.   
     
     
         13 . The device of  claim 12 , wherein the first conductive pad includes impurities of a first conductivity type, and the first channel structure comprises a channel impurity region having impurities of a second conductivity type and positioned adjacent to the first selection conductive patterns,
 wherein the bottom surface of the first conductive pad is separated from the channel impurity region.   
     
     
         14 . The device of  claim 12 , further comprising:
 a first string selection line connecting the first selection conductive patterns to each other; and   a second string selection line connecting the second selection conductive patterns to each other.   
     
     
         15 . The device of  claim 12 , further comprising:
 a dummy string line connected to the uppermost first selection conductive pattern of the plurality of first selection conductive patterns and the uppermost second selection conductive pattern of the plurality of second selection conductive patterns;   a first string selection line connected to the remaining selection conductive patterns of the plurality of first selection conductive patterns;   a second string selection line connected to the remaining second selection conductive patterns of the plurality of second selection conductive patterns.   
     
     
         16 . A three-dimensional semiconductor memory device, comprising:
 a substrate;   a vertical channel formed on the substrate;   a conductive pad formed on the vertical channel, wherein the conductive pad includes impurities of a first conductivity type;   a bit line formed on the conductive pad, wherein the bit line is electrically coupled to the conductive pad;   a plurality of word lines vertically formed on the substrate which is adjacent to the vertical channel; and   a plurality of selection conductive patterns vertically formed on the plurality of word lines,   wherein the vertical channel includes a channel impurity region and an offset region, wherein the offset region is interposed between the conductive pad and the channel impurity region, and wherein the channel impurity region has impurities of a second conductivity type.   
     
     
         17 . The three-dimensional semiconductor memory device of  claim 16 , wherein the bottom surface of the conductive pad is positioned between top and bottom surfaces of the uppermost selection conductive pad of the plurality of selection conductive pads. 
     
     
         18 . The three-dimensional semiconductor memory device of  claim 16 , wherein the uppermost selection conductive pad of the plurality of selection conductive pads horizontally overlap the conductive pad, and the remaining selection conductive pads horizontally overlap the channel impurity region. 
     
     
         19 . The three-dimensional semiconductor memory device of  claim 16 , wherein the first conductivity type is of n-type, and the second conductivity type is of p-type. 
     
     
         20 . The three-dimensional semiconductor memory device of  claim 16 , wherein the offset region, the conductive pad and the uppermost selection conductive pad constitutes a selection transistor, wherein the offset region serves as a source/drain of the selection transistor.