Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor

Abstract

An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.

1 . A system, comprising:
 an integrated circuit, comprising:
 an embedded logic analyzer block having an input for receiving a plurality of signals from one or more portions of a system under test for sampling and event triggering, and a trigger event block for detecting an occurrence of an event based in part upon the plurality of signals; and 
 a block having a first input coupled to the embedded logic analyzer block for receiving one or more of the plurality of signals, a second input coupled to the trigger event block for receiving a signal indicating the detection of the occurrence of the event, circuitry for generating a distinct set of one or more signals based upon the signal indicating the detection of the occurrence of the event, the distinct set of one or more signals being different from the plurality of signals appearing at the input of the embedded logic analyzer block and from the one or more of the plurality of signals received at the first input of the block, and an output for providing the generated distinct set of one or more signals to the embedded logic analyzer block as additional test signals for at least one of sampling thereof and event triggering. 
   
     
     
         2 . The system of  claim 1 , wherein the block is configurable to perform a function that is enabled based in part upon the detection of the occurrence of the event. 
     
     
         3 . The system of  claim 1 , wherein the distinct set of one or more signals is generated based in part upon at least one of the plurality of signals appearing at the input of the embedded logic analyzer block. 
     
     
         4 . The system of  claim 1 , wherein the block is configurable as an accumulator having an output which forms at least part of the output of the block and is provided to the embedded to logic analyzer circuitry at a second input thereof. 
     
     
         5 . The system of  claim 1 , wherein the embedded logic analyzer circuitry comprises a multiplexer block having an input coupled to the input of the embedded logic analyzer circuitry, the multiplexer block selecting at least one of the plurality of signals appearing at the input of the embedded logic analyzer circuitry for sampling or event triggering thereby, the trigger event block is coupled to an output of the multiplexer block, and the distinct set of one or more signals is provided to an input of the trigger event block. 
     
     
         6 . The system of  claim 1 , wherein the embedded logic analyzer circuitry comprises an output control block for selectively sampling at least one of the one or more signals received by the input of the embedded logic analyzer circuitry and the distinct set of one or more signals at the output of the block. 
     
     
         7 . The system of  claim 1 , wherein the block comprises field programmable circuitry. 
     
     
         8 . The system of  claim 1 , wherein the embedded logic analyzer circuitry comprises an input multiplexer block having a first input coupled to the input of the embedded logic analyzer circuitry and a second input coupled to the output of the block. 
     
     
         9 . The system of  claim 1 , wherein the distinct set of one or more signals is based on the one or more signals received at the first input of the block according to a predetermined function, the predetermined function being one of configurable and configured. 
     
     
         10 . A system, comprising:
 integrated circuitry, comprising:
 an embedded logic analyzer block having an input for receiving a plurality of signals from one or more portions of the system that is under test for sampling and event triggering, and a trigger event block for detecting an occurrence of an event based in part upon the plurality of signals; and 
 a block having a first input coupled to the embedded logic analyzer block for receiving one or more of the plurality of signals, a second input coupled to the trigger event block for receiving a signal indicating the detection of the occurrence of the event, circuitry for generating a distinct set of one or more signals based upon the signal indicating the detection of the occurrence of the event and one or more of the plurality of signals received at the first input of the block according to a predetermined function, the distinct set of one or more signals being different from the plurality of signals appearing at the input of the embedded logic analyzer block and from the one or more of the plurality of signals received at the first input of the block, and an output for providing the generated distinct set of one or more signals to the embedded logic analyzer block as additional test signals for at least one of sampling thereof and event triggering. 
   
     
     
         11 . The system of  claim 10 , wherein the predetermined function is configurable. 
     
     
         12 . The system of  claim 10 , wherein the predetermined function is configured. 
     
     
         13 . The system of  claim 10 , wherein the block is configurable to perform a function that is enabled based in part upon the detection of the occurrence of the event. 
     
     
         14 . The system of  claim 10 , wherein the block is configurable as an accumulator having an output which forms at least part of the output of the block and is provided to the logic analyzer circuitry for sampling thereof or event triggering. 
     
     
         15 . The system of  claim 10 , wherein the embedded logic analyzer circuitry comprises a multiplexer block coupled to the input of the embedded logic analyzer circuitry for selecting at least one of the plurality of signals appearing at the input of the embedded logic analyzer circuitry for sampling or event triggering thereby, the trigger event block is coupled to an output of the multiplexer block for detecting the event, and the distinct set of one or more signals is provided to an input of the trigger event block. 
     
     
         16 . The system of  claim 10 , wherein the embedded logic analyzer circuitry comprises an output control block for selectively sampling signals appearing at the first input of the embedded logic analyzer circuitry and at the output of the block. 
     
     
         17 . The system of  claim 10 , wherein the block comprises field programmable circuitry. 
     
     
         18 . The system of  claim 10 , wherein the embedded logic analyzer circuitry comprises an input multiplexer block having a first input coupled to the input of the embedded logic analyzer circuitry and a second input coupled to the output of the block. 
     
     
         19 . The system of  claim 10 , wherein the block comprises field programmed circuitry.