Semiconductor device and manufacturing method thereof

Abstract

A Si-on-half-insulator device and its manufacturing method are disclosed in this invention. In one embodiment, a horizontal insulating layer located below at least one of the source and drain regions is realized to reduce junction capacitance. In another embodiment, a horizontal insulating layer located below at least one of the source and drain regions and a vertical insulating layer located below at least one side surface of the gate are realized. The additional vertical insulating layer can reduce punch leakage. Further, a method of manufacturing the above semiconductor device is also disclosed, wherein the horizontal and vertical insulating layers are formed using an additional layer of epitaxially grown semiconductor material and isolating trenches.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a gate on a substrate;   source and drain regions located on opposite sides of the gate;   a horizontal insulating layer located substantially parallel to the surface of the substrate and below at least one of the source and drain regions.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising a vertical insulating layer located substantially vertical to the surface of the substrate and below a side surface of the gate. 
     
     
         3 . The semiconductor device according to  claim 2 , wherein the vertical insulating layer is lower than the source and drain regions. 
     
     
         4 . The semiconductor device according to  claim 3 , further comprising isolating trenches located on one side of the source and drain regions away from the gate. 
     
     
         5 . The semiconductor device according to  claim 4 , wherein the horizontal insulating layer intersects with the isolating trenches. 
     
     
         6 . The semiconductor device according to  claim 2 , wherein the horizontal insulating layer and the vertical insulating layer are in “ ” or “ ” form. 
     
     
         7 . The semiconductor device according to  claim 3 , wherein the horizontal insulating layer and the vertical insulating layer are in “ ” or “ ” form. 
     
     
         8 . A semiconductor device, comprising:
 a substrate having a protrusion and two flat portions on opposite sides of the protrusion;   at least one horizontal insulating layer located on at least one of the flat portions;   at least one vertical insulating layer located on at least a portion of at least one sidewall of the protrusion and intersecting with the horizontal insulating layer;   source and drain regions located on opposite sides of the protrusion; and   a gate on the protrusion.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein a height of the vertical insulating layer is less than a height of the protrusion. 
     
     
         10 . The semiconductor device according to  claim 8 , further comprising at least one isolating trench intersecting with the horizontal insulating layer and located away from the vertical insulating layer. 
     
     
         11 . The semiconductor device according to  claim 8 , wherein the source and drain regions are doped semiconductor layers grown on the flat portions. 
     
     
         12 . The semiconductor device according to  claim 8 , wherein at least one portion of the protrusion servers as a channel of semiconductor device. 
     
     
         13 . A semiconductor device, comprising:
 a gate on a substrate;   source and drain regions located on opposite sides of the gate;   a channel region between the source region and the drain region; and   at least one insulating structure on at least one side of the channel region, wherein the insulating structure comprises a horizontal portion and a vertical portion intersecting with the horizontal portion.   
     
     
         14 . The semiconductor device according to  claim 13 , wherein the horizontal portion of the insulating structure is in contact with the substrate and a height of the vertical portion of the insulating structure is less than a height of the source or drain region.