Methods for Manufacturing RFID Tags and Structures Formed Therefrom

Abstract

Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g., improved electrical characteristics) as compared to tags containing organic electronic devices.

What is claimed is: 
     
         1 . A device, comprising:
 a) an electrically active substrate;   b) a dielectric layer thereon, configured to insulate integrated circuitry from said metal-containing substrate;   c) a plurality of diodes and a plurality of thin film transistors on said dielectric layer, said diodes having at least one first semiconductor layer in common with said thin film transistors, said at least one first semiconductor layer being formed from a liquid-phase ink comprising silicon; and   d) a plurality of capacitors in electrical communication with at least some of said diodes, said plurality of capacitors having at least one metal layer in common with contacts to said diodes and thin film transistors.   
     
     
         2 . The device of  claim 1 , wherein said plurality of diodes have at least two different semiconductor layers in common with said plurality of thin film transistors. 
     
     
         3 . The device of  claim 2 , wherein a first of said at least two different semiconductor layers comprises a lightly doped inorganic semiconductor and a second of said at least two different semiconductor layers comprises a heavily doped inorganic semiconductor. 
     
     
         4 . The device of  claim 1 , wherein said plurality of diodes comprise diode-wired thin film transistors. 
     
     
         5 . The device of  claim 1 , further comprising an interlayer dielectric on or over said plurality of thin film transistors. 
     
     
         6 . The device of  claim 5 , further comprising a metallization layer over said interlayer dielectric, in electrical communication with said plurality of diodes and said plurality of thin film transistors. 
     
     
         7 . The device of  claim 6 , wherein said plurality of capacitors have an upper plate comprising said metallization layer. 
     
     
         8 . The device of  claim 1 , comprising a logic block and a memory block, said logic block communicating with said memory block and comprising a first subset of said thin film transistors, and said memory block comprising a first subset of said diodes and/or a second subset of said thin film transistors. 
     
     
         9 . The device of  claim 8 , further comprising an input/output control (sub)block comprising a third subset of said thin film transistors. 
     
     
         10 . The device of  claim 1 , wherein the plurality of thin film transistors is in a first region of the device and the plurality of diodes is in a second region of the device. 
     
     
         11 . The device of  claim 1 , wherein the electrically active substrate comprises a metal foil. 
     
     
         12 . An integrated circuit comprising:
 a) an electrically active substrate;   b) a dielectric layer on the substrate;   c) a plurality of first semiconductor layer elements formed from a liquid-phase ink comprising silicon, the plurality of first semiconductor layer elements comprising a thin film transistor channel region in a first region of the substrate and a first diode layer element in a second region of the substrate;   d) a plurality of second semiconductor layer elements comprising a second semiconductor layer in the first region of the substrate and a second diode layer element in the second region of the substrate; and   e) a plurality of metal elements on or over the first semiconductor layer elements and the second semiconductor layer elements, the metal elements comprising (i) a metal contact on or over the first and second semiconductor layer elements in the first region of the substrate, (ii) a metal gate over the thin film transistor channel region, (iii) a diode contact on or over the first and second semiconductor layer elements in the second region of the substrate, and (iv) a capacitor plate in a third region of the substrate.   
     
     
         13 . The integrated circuit of  claim 12 , wherein the electrically active substrate comprises a metal foil. 
     
     
         14 . The integrated circuit of  claim 12 , further comprising a capacitor in a third region of the substrate, wherein the plurality of first semiconductor layer elements comprise at least one lower capacitor plate and the plurality of metal elements comprise at least one upper capacitor plate in the third region of the substrate. 
     
     
         15 . A method of making an integrated circuit, comprising:
 a) forming a dielectric layer on an electrically active substrate;   b) forming, from a first silicon-containing ink, a plurality of first semiconductor elements in a first pattern on the dielectric layer, said first semiconductor layer elements comprising a thin film transistor channel region in a first region of the substrate and a first diode layer element in a second region of the substrate;   c) forming a plurality of second semiconductor layer elements different from said first semiconductor layer elements in a second pattern on at least one of said first semiconductor layer elements and said dielectric layer, said second semiconductor layer elements comprising a second semiconductor layer in the first region of the electrically active substrate and a second diode layer element in the second region of the electrically active substrate; and   d) forming a plurality of metal elements on or over the first semiconductor layer elements and the second semiconductor layer elements, the metal elements comprising a metal contact in the first region of the electrically active substrate, a metal gate over the thin film transistor channel region, a diode contact in the second region of the electrically active substrate, and a capacitor plate in a third region of the electrically active substrate.   
     
     
         16 . The method of  claim 15 , wherein said electrically active substrate comprises a metal foil. 
     
     
         17 . The method of  claim 15 , wherein at least one of said plurality of first and second semiconductor layer elements further comprises at least one capacitor plate in said third region of the electrically active substrate. 
     
     
         18 . The method of  claim 15 , further comprising, before forming said plurality of metal elements, growing an oxide on exposed surfaces of said first semiconductor layer elements and/or second semiconductor layer elements. 
     
     
         19 . The method of  claim 15 , wherein forming at least one of said first and second semiconductor layer elements comprises printing a corresponding silicon-containing ink. 
     
     
         20 . The method of  claim 15 , further comprising, before forming said plurality of metal elements, forming an interlayer dielectric on or over said first and second semiconductor layer elements, and forming a plurality of openings in said interlayer dielectric to expose surfaces of at least some of said first and second semiconductor layer elements.