Method for fabricating semiconductor device

Abstract

A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

What is claimed is: 
     
         1 . A method for fabricating metal gate transistor, comprising:
 providing a substrate having a NMOS region and a PMOS region;   forming a dummy gate on each of the NMOS region and the PMOS region respectively;   removing the dummy gates from each of the NMOS region and the PMOS region;   forming a n-type work function layer on the NMOS region and the PMOS region;   removing the n-type work function layer in the PMOS region;   forming a p-type work function layer on the NMOS region and the PMOS region; and   depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming the dummy gate on each of the NMOS region and the PMOS region respectively;   forming a spacer on the sidewall of each of the dummy gates;   forming a source/drain region in the substrate adjacent to the spacer;   forming a contact etch stop layer on the dummy gates;   forming an interlayer dielectric (ILD) layer on the contact etch stop layer; and   performing a replacement metal gate (RMG) process to form the dummy gates into metal gates.   
     
     
         3 . The method of  claim 2 , wherein the RMG process comprises:
 removing the dummy gates for forming a recess in each of the NMOS region and the PMOS region;   forming a high-k dielectric layer in the recesses and on the ILD layer;   forming a bottom barrier metal (BBM) layer on the high-k dielectric layer;   forming the n-type work function layer on the BBM layer of the NMOS region and the PMOS region;   removing the n-type work function layer in the PMOS region;   forming the p-type work function layer on the n-type work function layer of the NMOS region and the BBM layer of the PMOS region;   depositing the low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region; and   planarizing the low resistance metal layer, the p-type work function layer, and the n-type work function layer for forming a metal gate in each of the NMOS region and the PMOS region.   
     
     
         4 . The method of  claim 3 , wherein the BBM layer comprises TiSiN. 
     
     
         5 . A metal gate transistor, comprising:
 a substrate;   a metal gate on the substrate, wherein the metal gate comprises:
 a high-k dielectric layer; 
 a bottom barrier metal (BBM) layer on the high-k dielectric layer, wherein the BBM layer comprises TiSiN; 
 a TiN layer on the BBM layer; 
 a TiAl layer between the BBM layer and the TiN layer; and 
 a low resistance metal layer on the TiN layer; and 
   a source/drain region in the substrate adjacent to the metal gate.   
     
     
         6 . The metal gate transistor of  claim 5 , further comprising a spacer around the metal gate. 
     
     
         7 . The metal gate transistor of  claim 5 , wherein the metal gate transistor comprises a PMOS transistor. 
     
     
         8 . The metal gate transistor of  claim 5 , wherein the metal gate transistor comprises a NMOS transistor. 
     
     
         9 . The metal gate transistor of  claim 5 , wherein the high-k dielectric layer is U-shaped.