Process Mitigated Clock Skew Adjustment

Abstract

A device includes process mitigating timing (PMT) circuitry. The PMT circuitry allows for adjustment of a clock signal while compensating for process variation within the PMT circuitry. The PMT circuitry may include process mitigating buffer (PMB) circuitry. The PMB circuitry may utilize replica circuitry and a calibrated resistance to generate a calibrated bias voltage. The calibrated bias voltage may be used to drive component buffer circuits to create a calibrated current response. The calibrated current response may correspond to a selected output impedance for the component buffer circuits. The select output impedance may be used in concert with a variable capacitance to adjust a clock signal in manner that is independent of the process variation within the PMT circuitry.

What is claimed is: 
     
         1 . A circuit, comprising:
 a clock output node;   a clock input node;   replica circuitry comprising a calibrated resistor, the replica circuitry configured to:
 produce a reference voltage from a supply voltage input; and 
 generate a calibrated voltage using the reference voltage and calibrated resistor; 
   impedance buffer circuitry coupled to the clock input node and the clock output node, and configured to:
 receive the calibrated voltage; and 
 apply the calibrated voltage as a bias to produce a calibrated impedance coupled to the clock output node; and 
   capacitance buffer circuitry coupled to the clock input node and the clock output node, and comprising an output capacitance coupled to the calibrated impedance.