Two-terminal switching element having bidirectional switching characteristic, resistive memory cross-point array including same, and method for manufacturing two-terminal switching element and cross-point resistive memory array

Abstract

Provided are a two-terminal switching element having a bidirectional switching characteristic, a resistive memory cross-point array including the same, and methods for manufacturing the two-terminal switching element and the cross-point resistive memory array. The two-terminal switching element includes a first electrode and a second electrode. A pair of first conductive metal oxide semiconductor layers electrically connected to the first electrode and the second electrode, respectively, is provided. A second conductive metal oxide semiconductor layer is disposed between the first conductive metal oxide semiconductor layers. Therefore, the two-terminal switching element can show a symmetrical and bidirectional switching characteristic.

1 . A two-terminal switching element comprising:
 a first electrode;   a second electrode;   a pair of first conductivity type metal oxide semiconductor layers electrically connected to the first electrode and the second electrode; and   a second conductivity type metal oxide semiconductor layer disposed between the first conductivity type metal oxide semiconductor layers,   wherein any one of the first conductivity type and the second conductivity type is a P-type and the other is an N-type.   
     
     
         2 - 3 . (canceled) 
     
     
         4 . The element of  claim 1 , wherein the P-type metal oxide semiconductor layers each have a band gap of 3 eV or less. 
     
     
         5 . The element of  claim 1 , wherein the P-type metal oxide semiconductor layer has an atomic ratio of oxygen in a range 30% to 50% greater than a case in which a stoichiometric ratio is satisfied. 
     
     
         6 . The element of  claim 1 , wherein each P-type metal oxide semiconductor layer is CuO x  (1.1<x≦1.5) or CoO x  (1.1<x≦1.5). 
     
     
         7 . The element of  claim 1 , wherein the N-type metal oxide semiconductor layer is one metal oxide layer selected from the group consisting of ZnO, SnO 2 , In 2 O 3 , Ga 2 O 3 , InSnO, GaInO, ZnInO, ZnSnO, InGaZnO, TiO 2 , CeO 2 , Al 2 O 3 , Ta 2 O 5 , LaO 2 , NbO 2 , LiNbO 3 , BaSrTiO 3 , SrTiO 3 , ZrO 2 , SrZrO 3 , Nb-doped SrTiO 3 , Cr-doped SrTiO 3 , and Cr-doped SrZrO 3 . 
     
     
         8 . A resistive memory cross-point array comprising:
 a first end electrode;   a second end electrode;   a switching layer disposed between the first end electrode and the second end electrode and including a pair of first conductivity type metal oxide semiconductor layers and a second conductivity type metal oxide semiconductor layer disposed between the first conductivity type metal oxide semiconductor layers; and   a bipolar variable resistive layer disposed between the switching layer and the second end electrode,   wherein any one of the first conductivity type and the second conductivity type is a P-type and the other is an N-type.   
     
     
         9 . The array of  claim 8 , wherein the variable resistive layer is a magnetic tunnel junction (MTJ) structure or a resistance change memory layer. 
     
     
         10 . The array of  claim 8 , further comprising an intermediate electrode located between the switching layer and the variable resistive layer. 
     
     
         11 - 13 . (canceled) 
     
     
         14 . The array of  claim 8 , wherein the P-type metal oxide semiconductor layers each have a band gap of 3 eV or less. 
     
     
         15 . The array of  claim 8 , wherein the P-type metal oxide semiconductor layer has an atomic ratio of oxygen in a range 30% to 50% greater than a case in which a stoichiometric ratio is satisfied. 
     
     
         16 . The array of  claim 8 , wherein each P-type metal oxide semiconductor layer is CuO x  (1.1<x≦1.5) or CoO x  (1.1<x≦1.5). 
     
     
         17 . (canceled) 
     
     
         18 . A method of manufacturing a two-terminal switching element, comprising:
 forming a first conductivity type lower metal oxide semiconductor layer on a first electrode;   forming a second conductivity type metal oxide semiconductor layer on the first conductivity type lower metal oxide semiconductor layer;   forming a first conductivity type upper metal oxide semiconductor layer on the second conductivity type metal oxide semiconductor layer; and   forming a second electrode on the first conductivity type upper metal oxide semiconductor layer,   wherein any one of the first conductivity type and the second conductivity type is a P-type and the other is an N-type.   
     
     
         19 . The method of  claim 18 , further comprising annealing a resulting structure on which the second electrode is formed. 
     
     
         20 - 22 . (canceled) 
     
     
         23 . The method of  claim 18 , wherein the P-type metal oxide semiconductor layer has a band gap of 3 eV or less. 
     
     
         24 . The method of  claim 18 , wherein the P-type metal oxide semiconductor layer has an atomic ratio of oxygen in a range 30% to 50% greater than a case in which a stoichiometric ratio is satisfied. 
     
     
         25 . The method of  claim 18 , wherein the P-type metal oxide semiconductor layer is CuO x  (1.1<x≦1.5) or CoO x  (1.1<x≦1.5). 
     
     
         26 . (canceled) 
     
     
         27 . A method of manufacturing a resistive memory cross-point array, comprising:
 forming a switching layer including a first conductivity type lower metal oxide semiconductor layer, a second conductivity type metal oxide semiconductor layer, and a first conductivity type upper metal oxide semiconductor layer on a first end electrode;   forming a second end electrode on the switching layer; and   forming a variable resistive layer on the first end electrode before the switching layer is formed or on the switching layer before the second end electrode is formed,   wherein any one of the first conductivity type and the second conductivity type is a P-type and the other is an N-type.   
     
     
         28 . The method of  claim 27 , further comprising annealing a resulting structure on which the switching layer is formed. 
     
     
         29 - 31 . (canceled) 
     
     
         32 . The method of  claim 27 , further comprising forming an intermediate electrode between the switching layer and the variable resistive layer. 
     
     
         33 - 35 . (canceled) 
     
     
         36 . The method of  claim 27 , wherein the P-type metal oxide semiconductor layer has a band gap of 3 eV or less. 
     
     
         37 . The method of  claim 27 , wherein the P-type metal oxide semiconductor layer has an atomic ratio of oxygen in a range 30% to 50% greater than a case in which a stoichiometric ratio is satisfied. 
     
     
         38 . The method of  claim 27 , wherein the P-type metal oxide semiconductor layer is CuO x  (1.1<x≦1.5) or CoO x  (1.1<x≦1.5). 
     
     
         39 . (canceled)