Direct memory based ring oscillator (dmro) for on-chip evaluation of sram cell delay and stability

Abstract

A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an unmodified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

1 . A method of measuring the delay from wordline input to bitline output of a static
 random access memory (SRAM) cell, said method comprising:   providing a plurality of delay stage circuits configured to form a ring oscillator, each said delay stage comprising an SRAM cell;   guaranteeing an initial state of each delay stage circuit, wherein an incorrect state is corrected in a subsequent memory cycle;   generating a falling edge in the output of each delay stage circuit in response to a rising edge of said wordline input;   generating a rising edge in the output of each delay stage circuit in response to a falling edge of said wordline input; and   measuring the frequency of said ring oscillator thereby evaluating the wordline to bitline delay of said SRAM cell.   
     
     
         2 . The method according to  claim 1 , further comprising precharging the bitline to an appropriate charge level in response to the falling edge of said wordline. 
     
     
         3 . The method according to  claim 1 , further comprising monitoring stability of said SRAM cell by setting said SRAM cell to a predefined value and observing whether data in said SRAM cell changes or not. 
     
     
         4 . The method according to  claim 3 , wherein if cell data does change, generating a second output indicating existence of a stability problem. 
     
     
         5 . (canceled) 
     
     
         6 . The method according to  claim 1 , further comprising locating cell under test within a mini-array so as to emulate realistic capacitance and resistance conditions on said bitline. 
     
     
         7 . A direct memory ring oscillator (DMRO) circuit for measuring the wordline to bitline delay of a static random access memory (SRAM) cell, comprising:
 a plurality of delay stage circuits, each delay stage circuit comprising:
 an SRAM cell; 
 circuitry operative to guarantee an initial state of said delay stage circuit, wherein an incorrect state is corrected in a subsequent memory cycle, to generate a falling edge of the output of said delay stage circuit in response to the rising edge of the wordline, and to generate a rising edge of the output of said delay stage circuit in response to the falling edge of the wordline; 
   wherein measuring the frequency of said DMRO corresponds to the wordline to bitline delay of said SRAM cell.   
     
     
         8 . The circuit according to  claim 7 , further comprising circuitry operative to precharge the bitline to an appropriate charge level in response to the falling edge of said wordline. 
     
     
         9 . The circuit according to  claim 7 , further comprising circuitry operative to monitor stability of said SRAM cell by setting said SRAM cell to a predefined value and observing whether data in said SRAM cell changes or not. 
     
     
         10 . The circuit according to  claim 9 , further comprising circuitry operative to generate a second output indicating a stability problem in response to detecting a change in said predefined value. 
     
     
         11 . (canceled) 
     
     
         12 . The circuit according to  claim 7 , further comprising placing the cell under test in a mini-array of SRAM cells so as to emulate realistic conditions as much as possible. 
     
     
         13 . A method of measuring the delay and stability of a static random access memory (SRAM) cell, said method comprising:
 incorporating the delay from a wordline input to a bitline output of said SRAM into delay stage circuits of a ring oscillator;   guaranteeing an initial state of each delay stage circuit, wherein an incorrect state is corrected in a subsequent memory cycle; and   measuring the frequency of oscillation of said ring oscillator, wherein said frequency corresponds to said wordline to bitline delay.   
     
     
         14 . The method according to  claim 13 , further comprising generating a falling edge in the output of each delay stage circuit in response to a rising edge of said wordline input, and generating a rising edge in the output of each delay stage circuit in response to a falling edge of said wordline input. 
     
     
         15 . The method according to  claim 13 , further comprising precharging the bitline to an appropriate charge level in response to the falling edge of said wordline. 
     
     
         16 . The method according to  claim 13 , further comprising monitoring stability of said SRAM cell by setting said SRMA cell to a predefined value and observing whether data in said SRAM cell changes or not. 
     
     
         17 . The method according to  claim 16 , wherein if cell data does change, generating a second output indicating existence of a random read instability problem. 
     
     
         18 . (canceled) 
     
     
         19 . The method according to  claim 13 , further comprising locating the cell under test within a mini-array so as to emulate realistic conditions of operation. 
     
     
         20 . The method according to  claim 13 , further comprising wherein drop in frequency indicates read instability in said SRAM cell.