Virtual memory module

Abstract

A memory controller of a mass memory device determining that a memory operation has been initiated which involves the mass memory device, and in response dynamically checks for available processing resources of a host device that is operatively coupled to the mass memory device and thereafter puts at least one of the available processing resources into use for performing the memory operation. In various non-limiting examples: the available processing resources may be a core engine of a multi-core CPU, a DPS or a graphics processor; central processing unit; a digital signal processor; and a graphics processor; and it may also be dynamically checked whether memory resources of the host are available and those can be similarly put into use (e.g., write data to a DRAM of the host, process data in the DRAM with the host DSP, then write the processed data to the mass memory device).

1 - 20 . (canceled) 
     
     
         21 . A memory device comprising:
 an interface operable to couple the memory device to a host device; and   a memory controller operable to:
 in relation to a memory operation, determine available processing resources of the host device by at least checking one or more registers of the memory device, the one or more registers operable to store host device resource availability information that is updateable by the host device; and 
 transmit a request, via the interface, for the host device to perform at least part of the memory operation using at least one available processing resource of the available processing resources, wherein the at least one available processing resource comprises a processing entity of the host device and the request is for the processing entity to process data read from the memory device to a memory of the host device. 
   
     
     
         22 . The memory device according to  claim 21 , wherein the processing entity comprises at least one of:
 a core engine of a multi-core central processing unit;   a digital signal processor (DSP); or   a graphics processor.   
     
     
         23 . The memory device according to  claim 21 , wherein the processing to be performed by the processing entity comprises error correction. 
     
     
         24 . The memory device according to  claim 21 , wherein the memory controller is further operable to:
 determine available memory resources of the host device; and   transmit another request, via the interface, for the host device to perform at least another part of the memory operation using at least one available memory resource of the available memory resources of the host device, wherein the at least one available memory resource comprises the memory of the host device which is useable to temporarily store the data read from the memory device.   
     
     
         25 . The memory device according to  claim 21 , wherein the memory of the host device comprises a dynamic random access memory (DRAM). 
     
     
         26 . The memory device according to  claim 21 , wherein the memory controller is further operable to transmit, via the interface, another request for the host device to update the one or more registers of the memory device. 
     
     
         27 . The memory device according to  claim 21 , wherein the determining the available processing resources further comprises checking an access command received from the host device, the access command indicating at least part of the available processing resources of the host device. 
     
     
         28 . The memory device according to  claim 21 , wherein the memory device comprises at least one of:
 a memory on-board the host device;   a memory removable from the host device; or   a solid state drive (SSD).   
     
     
         29 . A method comprising:
 in relation to a memory operation, determining, by a memory device, available processing resources of a host device that is operatively coupled to the memory device by at least checking one or more registers of the memory device, the one or more registers operable to store host device resource availability information that is updateable by the host device; and   transmitting, by the memory device, a request for the host device to perform at least part of the memory operation using at least one available processing resource of the available processing resources, wherein the at least one available processing resource comprises a processing entity of the host device and the request is for the processing entity to process data read from the memory device to a memory of the host device.   
     
     
         30 . The method according to  claim 29 , wherein the processing entity comprises at least one of:
 a core engine of a multi-core central processing unit;   a digital signal processor (DSP); or   a graphics processor.   
     
     
         31 . The method according to  claim 29 , wherein the processing to be performed by the processing entity comprises error correction. 
     
     
         32 . The method according to  claim 29 , wherein the memory of the host device comprises a dynamic random access memory (DRAM). 
     
     
         33 . The method according to  claim 29 , further comprising transmitting, by the memory device, another request for the host device to update the one or more registers of the memory device. 
     
     
         34 . The method according to  claim 29 , further comprising:
 determining, by the memory device, available memory resources of the host device; and   transmitting, by the memory device, another request for the host device to perform at least another part of the memory operation using at least one available memory resource of the available memory resources of the host device, wherein the at least one available memory resource comprises the memory of the host device which is useable to temporarily store the data read from the memory device.   
     
     
         35 . One or more non-transitory computer readable media storing instructions that, when executed, cause a memory device to:
 in relation to a memory operation, determine available processing resources of a host device that is operatively coupled to the memory device by at least checking one or more registers of the memory device, the one or more registers operable to store host device resource availability information that is updateable by the host device; and   transmit a request for the host device to perform at least part of the memory operation using at least one available processing resource of the available processing resources, wherein the at least one available processing resource comprises a processing entity of the host device and the request is for the processing entity to process data read from the memory device to a memory of the host device.   
     
     
         36 . The one or more non-transitory computer readable media according to  claim 35 , wherein the processing entity comprises at least one of:
 a core engine of a multi-core central processing unit;   a digital signal processor (DSP); or   a graphics processor.   
     
     
         37 . The one or more non-transitory computer readable media according to  claim 35 , wherein the processing to be performed by the processing entity comprises error correction. 
     
     
         38 . The one or more non-transitory computer readable media according to  claim 35 , wherein the memory of the host device comprises a dynamic random access memory (DRAM). 
     
     
         39 . The one or more non-transitory computer readable media according to  claim 35 , wherein the instructions further cause the memory device to transmit another request for the host device to update the one or more registers of the memory device. 
     
     
         40 . The one or more non-transitory computer readable media according to  claim 35 , wherein the instructions further cause the memory device to:
 determine available memory resources of the host device; and   transmit another request for the host device to perform at least another part of the memory operation using at least one available memory resource of the available memory resources of the host device, wherein the at least one available memory resource comprises the memory of the host device which is useable to temporarily store the data read from the memory device.   
     
     
         41 . A host device comprising:
 a processing entity operable to:
 update one or more registers of a memory device with host resource availability information so the host resource availability information is accessible by the memory device; 
 receive a request from the memory device to perform at least part of a memory operation using at least one available processing resource of the host device; and 
 perform the at least part of the memory operation using the at least one available processing resource based at least in part on the received request. 
   
     
     
         42 . The host device according to  claim 41 , wherein the processing entity is further operable to:
 receive another request from the memory device to perform at least another part of the memory operation using at least one available memory resource of the host device; and   perform the at least another part of the memory operation using the at least one available memory resource based at least in part on the another received request.   
     
     
         43 . The host device according to  claim 41 , wherein the at least one available processing resource is determined via checking the host resource availability information stored in the one or more registers of the memory device. 
     
     
         44 . The host device according to  claim 41 , wherein:
 the memory operation comprises a read operation; and   the request is for the at least one available processing resource to process data read from the memory device to a memory of the host device.   
     
     
         45 . The host device according to  claim 41 , wherein:
 the memory operation comprises a write operation; and   the request is for the at least one available processing resource to process data written temporarily to a memory of the host device prior to writing the data from the host device to a memory of the memory device.   
     
     
         46 . The host device according to  claim 41 , wherein the at least one available processing resource comprises at least one of:
 a core engine of a multi-core central processing unit;   a digital signal processor (DSP); or   a graphics processor.   
     
     
         47 . The host device according to  claim 41 , wherein the processing to be performed by the at least one available processing resource comprises error correction.