3d flash memory device having different dummy word lines and data storage devices including same

Abstract

A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.

What is claimed is: 
     
         1 . A nonvolatile memory device comprising:
 a plurality of cell strings including a first cell string, the first cell string including a string selection transistor, a first dummy cell, a plurality of nonvolatile memory cells, a second dummy cell and a ground selection transistor that are serially connected in order and are stacked on or above a substrate in a direction that is perpendicular to the substrate, the first dummy cell being adjacent to the string selection transistor, the ground selection transistor being adjacent to the second dummy cell;   a string select line connected the string selection transistor;   a ground select line connected the ground selection transistor;   a plurality of main word lines connected to the plurality of nonvolatile memory cells respectively;   a first dummy word line connected to the first dummy cell; and   a second dummy word line connected to the second dummy cell;   wherein a first separation length between the string select line and the first dummy word line is different from a second separation length between the ground select line and the second dummy word line.   
     
     
         2 . The nonvolatile memory device of  claim 1 , the first separation length is greater than the second separation length. 
     
     
         3 . The nonvolatile memory device of  claim 2 , wherein the plurality of main word lines include a first main word line and a second main word line adjacent to the first main word line, and
 the second separation length is greater than a third separation length between the first main word line and the second main word line.   
     
     
         4 . The nonvolatile memory device of  claim 3 , wherein the first cell string includes a third dummy cell adjacent to the first dummy cell and disposed between the first dummy cell and the plurality of nonvolatile memory cells, the third dummy cell being adjacent to the a first memory cell among the plurality of nonvolatile memory cells. 
     
     
         5 . The nonvolatile memory device of  claim 4 , wherein the first separation length is greater than a fourth separation length between a third dummy word line connected to the third dummy cell and a first main word line connected to the first memory cell. 
     
     
         6 . The nonvolatile memory device of  claim 5 , wherein the second separation length is greater than the fourth separation length. 
     
     
         7 . The nonvolatile memory device of  claim 6 , wherein the fourth separation length is equal to the third separation length. 
     
     
         8 . The nonvolatile memory device of  claim 4 , wherein the plurality of cell strings including a second cell string,
 the first cell string and the second cell string are connected to a first bit line, the plurality of main word lines and a source line, and   the second cell string is connected to a second string selection line.   
     
     
         9 . The nonvolatile memory device of  claim 8 , further comprising:
 a page buffer circuit configured to apply a program bit line voltage or a program inhibit voltage to the first bit line during a program operation; and   a voltage generator configured to apply a source line voltage to the source line during the program operation, and to apply a program voltage to a first main word line among the plurality of main word lines that is connected to the first memory cell;   wherein the program bit line voltage, the source line voltage and the program voltage are applied to the first cell string simultaneously, and   the source line voltage is higher than the program bit line voltage.   
     
     
         10 . The nonvolatile memory device of  claim 1 , further comprising an address decoder configured to apply a turn-off voltage to the string selection line thereby to turn off the string selection transistor, configured to apply the turn-off voltage to the ground selection line, and configured to apply a plurality of pass voltages to unselected word lines among the plurality of main word lines thereby to boost a channel of the first cell string,
 wherein the first separation length is greater than the second separation length thereby to cause an electric field difference between a first electric field and a second electric field to be reduced, the first electric field existing between the boosted channel of the first cell string and the first bit line, the second electric field existing between the boosted channel of the first cell string and the source line.   
     
     
         11 . The nonvolatile memory device of  claim 10 , wherein the plurality of main word lines include a first main word line and a second main word line adjacent to the first main word line, and
 the second separation length is greater than a third separation length between the first main word line and the second main word line.   
     
     
         12 . A nonvolatile memory device comprising:
 a plurality of cell strings including a first cell string, the first cell string including a string selection transistor, a first dummy cell, a plurality of nonvolatile memory cells, a second dummy cell and a ground selection transistor that are serially connected in order and are stacked on or above a substrate in a direction that is perpendicular to the substrate, the first dummy cell being adjacent to the string selection transistor, the ground selection transistor being adjacent to the second dummy cell;   a string select line connected the string selection transistor;   a ground select line connected the ground selection transistor;   a plurality of main word lines connected to the plurality of nonvolatile memory cells respectively;   a first dummy word line connected to the first dummy cell;   a second dummy word line connected to the second dummy cell;   wherein a first width of the first dummy word line is different from the a second width of the second dummy word line.   
     
     
         13 . The nonvolatile memory device of  claim 12 , the first width is greater than the second width. 
     
     
         14 . The nonvolatile memory device of  claim 13 , wherein the plurality of main word lines include a first main word line,
 the first width is greater than a third width of the first main word line.   
     
     
         15 . The nonvolatile memory device of  claim 14 , wherein the second width is equal to the third width. 
     
     
         16 . The nonvolatile memory device of  claim 14 , wherein the plurality of cell strings including a second cell string,
 the first cell string and the second cell string are connected to a first bit line, the plurality of main word lines and a source line, and   the second cell string is connected to a second string selection line.   
     
     
         17 . The nonvolatile memory device of  claim 16 , further including:
 a page buffer circuit configured to apply a program bit line voltage or a program inhibit voltage to the first bit line during a program operation; and   a voltage generator configured to apply a source line voltage to the source line during the program operation, to apply a program voltage to a first main word line connected to the first memory cell,   wherein the program bit line voltage, the source line voltage and the program voltage is applied to the first cell string simultaneously, and   the source line voltage is higher than the program bit line voltage.   
     
     
         18 . The nonvolatile memory device of  claim 16 , wherein the first cell string includes a third dummy cell adjacent to the first dummy cell. 
     
     
         19 . The nonvolatile memory device of  claim 12 , further comprising an address decoder configured to apply a turn-off voltage to the string selection line thereby to turn off the string selection transistor, configured to apply the turn-off voltage to the ground selection line, and configured to apply a plurality of pass voltages to unselected word lines among the plurality of main word lines thereby to boost a channel of the first cell string,
 wherein the first width is greater than the second width thereby to cause an electric field difference between a first electric field and a second electric field to be reduced, the first electric field existing between the boosted channel of the first cell string and the first bit line, the second electric field existing between the boosted channel of the first cell string and the source line.   
     
     
         20 . The nonvolatile memory device of  claim 12 , wherein the plurality of main word lines include a first main word line,
 the first width is greater than a third width of the first main word line.   
     
     
         21 . A method of operating a memory system including a memory controller and a nonvolatile memory device, the nonvolatile memory device including a plurality of cell strings including a first cell string and a second cell string, each of the plurality of cell strings including a string selection transistor, a first dummy cell, a plurality of nonvolatile memory cells, a second dummy cell and a ground selection transistor that are serially connected in order and are stacked on or above a substrate in a direction that is perpendicular to the substrate, the first dummy cell being adjacent to the string selection transistor, the ground selection transistor being adjacent to the second dummy cell, the method comprising:
 providing, by the memory controller, a program command and an address to the nonvolatile memory device;   programming a first memory cell among the plurality of nonvolatile memory cells of the first cell string corresponding to the address in response to the program command by applying a program word line voltage to a first word line connected to the first memory cell and a program bit-line voltage to a first bit-line, the first cell string and the second cell string being connected to the first bit-line; and   program-inhibiting the plurality of nonvolatile memory cells of the second cell string including a second memory cell that is connected to the first word line;   wherein the program-inhibiting the plurality of nonvolatile memory cells of the second cell string further comprising:
 applying a source line voltage higher than the program bit-line voltage to a source line, the first cell string and the second cell string being connected to the source line; 
 applying a ground voltage to a second string select line connected to the string selection transistor of the second cell string; 
 applying the ground voltage to a ground select line connected to the ground selection transistor of the second cell string; and 
 boosting a channel of the second cell string by applying a plurality of pass voltages to unselected word lines, a first dummy word line and a second dummy word line, the unselected word lines being connected to unselected memory cells among the plurality of nonvolatile memory cells of the second cell string, the first dummy word line being connected to the first dummy cell of the first cell string and the first dummy cell of the second cell string, the second dummy word line being connected to the second dummy cell of the first cell string and the second dummy cell of the second cell string, and 
   wherein a first separation length between the first string select line and the first dummy word line is different from the a second separation length between the ground select line and the second dummy word line.   
     
     
         22 . The method of  claim 21 , wherein the first separation length is greater than the second separation length thereby to cause an electric field difference between a first electric field and a second electric field to be reduced, the first electric field existing between the boosted channel of the second cell string and the first bit line, the second electric field existing between the boosted channel of the second cell string and the source line. 
     
     
         23 . The method of  claim 22 , wherein the unselected word lines includes a first unselected word line and a second unselected word line adjacent to the first unselected word line, and
 the second separation length is greater than a third separation length between the first unselected word line and the second unselected word line.   
     
     
         24 . The method of  claim 23 , wherein the second cell string includes a third dummy cell adjacent to the first dummy cell and disposed between the first dummy cell of the second cell string and the plurality of nonvolatile memory cells of the second cell string, the third dummy cell being adjacent to a third memory cell among the plurality of nonvolatile memory cells of the second cell string. 
     
     
         25 . The method of  claim 24 , wherein the first separation length is greater than a fourth separation length between a third dummy word line connected to the third dummy cell and the first unselected word line connected to the third memory cell. 
     
     
         26 . The method of  claim 25 , wherein the second separation length is greater than the fourth separation length. 
     
     
         27 . A method of operating a memory system including a memory controller and a nonvolatile memory device, the nonvolatile memory device including a plurality of cell strings including a first cell string and a second cell string, each of the plurality of cell strings including a string selection transistor, a first dummy cell, a plurality of nonvolatile memory cells, a second dummy cell and a ground selection transistor that are serially connected in order and are stacked on or above a substrate in a direction that is perpendicular to the substrate, the first dummy cell being adjacent to the string selection transistor, the ground selection transistor being adjacent to the second dummy cell, the method comprising:
 providing, by the memory controller, a program command and an address to the nonvolatile memory device;   programming a first memory cell among the plurality of nonvolatile memory cells of the first cell string corresponding to the address in response to the program command by applying a program word line voltage to a first word line connected to the first memory cell and a program bit-line voltage to a first bit-line, the first cell string and the second cell string being connected to the first bit-line; and   program-inhibiting the plurality of nonvolatile memory cells of the second cell string including a second memory cell, the second memory cell being connected to the first word line;   wherein the program-inhibiting the plurality of nonvolatile memory cells of the second cell string further comprising:
 applying a source line voltage higher than the program bit-line voltage 
 to a source line, the first cell string and the second cell string being connected to the source line; 
 applying a ground voltage to a second string select line connected to the string selection transistor of the second cell string; 
 applying the ground voltage to a ground select line connected to the ground selection transistor of the second cell string; 
 boosting a channel of the second cell string by applying a plurality of pass voltages to unselected word lines, a first dummy word line and a second dummy word line, the unselected word lines being connected to unselected memory cells among the plurality of nonvolatile memory cells of the second cell string, the first dummy word line being connected to the first dummy cell of the first cell string and the first dummy cell of the second cell string, the second dummy word line being connected to the second dummy cell of the first cell string and the second dummy cell of the second cell string; 
   wherein a first width of the first dummy word line is different from the a second width of the second dummy word line.   
     
     
         28 . The method of  claim 27 , wherein the first width is greater than the second width thereby to cause an electric field difference between a first electric field and a second electric field to be reduced, the first electric field existing between the boosted channel of the second cell string and the first bit line, the second electric field existing between the boosted channel of the second cell string and the source line. 
     
     
         29 . The method of  claim 28 , wherein the unselected word lines includes a first unselected word line,
 the first width is greater than a third width of the first unselected word line.   
     
     
         30 . The method of  claim 29 , wherein the second width is equal to the third width.