Method for processing a carrier and a carrier

Abstract

A method for processing a carrier may include forming at least one recess structure at least one of over and in the carrier; and annealing the at least one recess structure such that at least one hollow chamber is formed by material of the at least one recess structure, wherein the at least one hollow chamber may form an optical alignment structure.

What is claimed is: 
     
         1 . A carrier comprising:
 at least one optical alignment structure formed by at least one hollow chamber arranged in the carrier.   
     
     
         2 . The carrier according to  claim 1 ,
 wherein the carrier is a silicon wafer and wherein the at least one hollow chamber is arranged in the silicon wafer.   
     
     
         3 . The carrier according to  claim 2 ,
 wherein the at least one hollow chamber is completely surrounded by silicon.   
     
     
         4 . The carrier according to  claim 1 ,
 wherein the optical alignment structure is configured to be detectable by infrared light.   
     
     
         5 . The carrier according to  claim 1 ,
 wherein the at least one hollow chamber is covered with a silicon layer having a thickness in the range from about 0.5 μm to about 50 μm.   
     
     
         6 . The carrier according to  claim 5 ,
 wherein the silicon layer comprises doped silicon.   
     
     
         7 . The carrier according to  claim 5 ,
 wherein the silicon layer is an epitaxial silicon layer.   
     
     
         8 . A carrier comprising:
 at least one optical alignment structure formed by at least two hollow chambers arranged in the carrier, wherein a size of a first hollow chamber of the at least two hollow chambers is greater than a size of a second hollow chamber of the at least two hollow chambers.   
     
     
         9 . The carrier according to  claim 8 ,
 wherein each of the at least two hollow chambers has a height in the range from about 0.5 μm to about 1.5 μm.   
     
     
         10 . The carrier according to  claim 8 ,
 wherein each of the at least two hollow chambers has a width in the range from about 1 μm to about 20 μm.   
     
     
         11 . The carrier according to  claim 8 ,
 wherein each of the at least two hollow chambers has a height in the range from about 0.5 μm to about 1.5 μm and a width in a range from about 1 μm to about 20 μm.   
     
     
         12 . The carrier according to  claim 8 ,
 wherein each of the at least two hollow chambers is surrounded by silicon.   
     
     
         13 . The carrier according to  claim 12 ,
 wherein each of the at least two hollow chambers is completely surrounded by silicon.   
     
     
         14 . The carrier according to  claim 8 ,
 wherein the carrier is a silicon wafer and wherein the at least two hollow chambers are arranged in the silicon wafer.   
     
     
         15 . The carrier according to  claim 14 ,
 wherein the at least two hollow chambers are formed in a kerf region of the silicon wafer.   
     
     
         16 . The carrier according to  claim 8 ,
 wherein the at least two hollow chambers are covered with a silicon layer, the silicon layer having a thickness in the range from about 0.5 μm to about 50 μm.   
     
     
         17 . The carrier according to  claim 16 ,
 wherein the silicon layer comprises doped silicon.   
     
     
         18 . The carrier according to  claim 8 ,
 wherein the optical alignment structure is configured to be detectable by infrared light.   
     
     
         19 . The carrier according to  claim 18 ,
 wherein the optical alignment structure is configured to be detectable by an infrared alignment tool using infrared light with a wavelength in the range from about 1000 nm to about 1200 nm.   
     
     
         20 . A wafer comprising:
 at least one optical alignment structure formed by a plurality of hollow chambers arranged in the wafer, wherein a size of a first hollow chamber of the plurality of hollow chambers is greater than a size of a second hollow chamber of the plurality of hollow chambers.