Semiconductor storage device

Abstract

A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality of sense amplifiers respectively correspond to the bit lines and are configured to detect data stored in the memory cells via a bit line selected from among the corresponding bit lines. A plurality of read latch parts correspond to the sense amplifiers, respectively, and are configured to latch data detected by the corresponding sense amplifiers. A plurality of read global data buses are connected to the read latch parts, respectively, and are configured to consecutively transmit data latched by the read latch parts at a time of a data read operation.

1 . A semiconductor storage device comprising:
 a plurality of bit lines;   a plurality of word lines;   a plurality of memory cells respectively connected to the bit lines and the word lines;   a plurality of sense amplifiers configured to detect data stored in the memory cells via the bit lines;   a row decoder selecting one of the word lines; and   a column decoder selecting one of the bit lines, wherein   after an active command is received by the device at a time when receiving a clock, a read command is received by the device at a time when receiving next clock.