Integrated circuit layout structure

Abstract

An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes at least one or more first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type.

1 . An integrated circuit layout structure having dual-height standard cells, comprising:
 at least a first standard cell having a first cell height, the first standard cell comprising at least one or more first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell, the first doped region having a first conductivity type, the second doped regions having a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other; and   at least a second standard cell having a second cell height, the second cell height being one half of the first cell height.   
     
     
         2 . The integrated circuit layout structure having the dual-height standard cells according to  claim 1 , wherein an area of the first doped region is smaller than an area of the second doped regions. 
     
     
         3 . The integrated circuit layout structure having the dual-height standard cells according to  claim 1 , wherein the second standard cell further comprises at least one or more third doped region comprising the first conductivity type and at least one or more fourth doped region comprising the second conductivity type. 
     
     
         4 . The integrated circuit layout structure having the dual-height standard cells according to  claim 1 , further comprising a first conductor extending across the middle of the first standard cell and a middle of the first doped region. 
     
     
         5 . The integrated circuit layout structure having the dual-height standard cells according to  claim 4 , further comprising a pair of second conductors respectively extending across a top and a bottom of the first standard cell, and one of the second conductors extending across a top or a bottom of the second standard cell. 
     
     
         6 . The integrated circuit layout structure having the dual-height standard cells according to  claim 5 , wherein the first conductor extends across the top or the bottom of the second standard cell opposite to the second conductor. 
     
     
         7 . The integrated circuit layout structure having the dual-height standard cells according to  claim 1 , wherein the first standard cell and the second standard cell comprise pseudo n-channel metal-oxide-semiconductor (pseudo-NMOS) logic cell, dynamic logic cell, domino logic cell, or fully differential logic cell. 
     
     
         8 . The integrated circuit layout structure having the dual-height standard cells according to  claim 7 , wherein the first standard cell comprises at least a p-channel metal-oxide-semiconductor (PMOS) transistor and a plurality of NMOS transistors, and the second standard cell comprises at least a PMOS transistor and a plurality of NMOS transistors. 
     
     
         9 . The integrated circuit layout structure having the dual-height standard cells according to  claim 7 , wherein an amount of the PMOS transistor in the second standard cell is equal to an amount of the PMOS in the first standard cell. 
     
     
         10 . The integrated circuit layout structure having the dual-height standard cells according to  claim 9 , wherein a logic operation maximum of the first standard cell is two times of the second standard cell. 
     
     
         11 . An integrated circuit layout structure having dual-height standard cells, comprising:
 at least a first standard cell having a first cell height, the first standard cell comprising a plurality of first doped regions and at least one or more second doped region, the first doped regions having a first conductivity type, the second doped region having a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other;   at least a second standard cell having a second cell height, the second cell height being one half of the first cell height; and   a first conductor extending across a middle of the first standard cell,   wherein the first doped regions are separately formed and spaced apart from each other at two sides of the first conductor.   
     
     
         12 . The integrated circuit layout structure having the dual-height standard cells according to  claim 11 , wherein the second standard cell further comprises at least one or more third doped region comprising the first conductivity type and at least one or more fourth doped region comprising the second conductivity type. 
     
     
         13 . The integrated circuit layout structure having the dual-height standard cells according to  claim 12 , wherein a length of the first doped regions is larger than a length of the third doped region. 
     
     
         14 . The integrated circuit layout structure having the dual-height standard cells according to  claim 11 , wherein the first standard cell further comprises a plurality of first gate electrodes and the second standard cell further comprises a plurality of second gate electrodes. 
     
     
         15 . The integrated circuit layout structure having the dual-height standard cells according to  claim 14 , further comprising a plurality of second gate connectors formed in between and electrically connecting the second gate electrodes, the second gate electrodes and the second gate connectors comprise a same material formed in a same layer. 
     
     
         16 . The integrated circuit layout structure having the dual-height standard cells according to  claim 15 , wherein the first standard cell comprises no gate connector. 
     
     
         17 . The integrated circuit layout structure having the dual-height standard cells according to  claim 15 , wherein the first standard cell comprises a plurality of first gate connectors formed in between and electrically connecting the first gate electrodes, the first gate electrodes and the first gate connectors comprise a same material formed in a same layer, and an amount of the first gate connectors is smaller than an amount of the second gate connectors. 
     
     
         18 . The integrated circuit layout structure having the dual-height standard cells according to  claim 11 , further comprising a pair of second conductors extending across a top and a bottom of the first standard cell. 
     
     
         19 . The integrated circuit layout structure having the dual-height standard cells according to  claim 18 , wherein one of the second conductors extends across a top or a bottom of the second standard cell. 
     
     
         20 . The integrated circuit layout structure having the dual-height standard cells according to  claim 19 , wherein the first conductor extends across the top or the bottom of the second standard cell opposite to the second conductor.