Clock correction circuit and clock correction method

Abstract

An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

What is claimed is: 
     
         1 . A real-time clock circuit comprising:
 a clock correction circuit that generates a first clock from a second clock having a frequency error; and   a correction register that stores a value corresponding to the frequency error,   wherein a target frequency of the first clock is 1 Hz,   wherein a frequency of the second clock is substantially equal to 32.768 KHz,   wherein the value is translated to a correction value per one second, and   wherein the clock correction circuit adjusts the first clock at an interval of one second using the correction value.   
     
     
         2 . The real-time clock circuit according to  claim 1 , when the frequency error is 0.95 ppm, and the correction value is 2̂ −20  second. 
     
     
         3 . The real-time clock circuit according to  claim 1 , wherein the clock correction circuit adjusts the first clock at interval of one second using the correction value by a third clock. 
     
     
         4 . The real-time clock circuit according to  claim 3 , wherein a frequency of the third clock is higher than 32.768 KHz.