Cryptographic hashing circuitry having improved scheduling efficiency

Abstract

Cryptographic hashing circuitry such as mining circuitry used to mine digital currency may be formed on an integrated circuit. The hashing circuitry may include sequential rounds of register and logic circuitry that perform operations of a cryptographic protocol. A final hash value output by the hashing circuitry may include hash values stored at previous rounds of the cryptographic hashing circuitry. The hashing circuitry may be formed with only two registers per round, thereby optimizing chip area consumption. The hashing circuitry may perform sequential rounds of cryptographic hashing based on an initial hash value and multiple message words. One or more message registers may store the message words. Control circuitry may selectively route the message words from the message register to the hashing circuitry using pointers. If desired, the message registers may be replaced by one or more arrays of memory elements read using row and column pointers.

What is claimed is: 
     
         1 . Cryptographic hashing circuitry on an integrated circuit, comprising:
 a first register that stores a first hash value;   logic circuitry that is configured to generate a second hash value based on at least the stored first hash value; and   a second register that stores the second hash value, wherein the second register is configured to output the stored second hash value as part of a hash output value, the first register is configured to directly output the stored first hash value as part of the hash output value, and the first hash value is different from the second hash value.   
     
     
         2 . The cryptographic hashing circuitry defined in  claim 1 , further comprising:
 a third register that stores a third hash value, wherein the logic circuitry is configured to generate the first hash value based on at least the stored third hash value, wherein the third register is configured to directly output the stored third hash value as a part of the hash output value, and wherein the third hash value is different from the first and second hash values.   
     
     
         3 . The cryptographic hashing circuitry defined in  claim 2 , further comprising:
 a fourth register that stores a fourth hash value, wherein the logic circuitry is configured to generate the third hash value based on at least the stored fourth hash value, wherein the fourth register is configured to directly output the stored fourth hash value as part of the hash output value, and wherein the fourth hash value is different from the first, second, and third hash values.   
     
     
         4 . The cryptographic hashing circuitry defined in  claim 3 , wherein the hash output value comprises a 256-bit hash output value and wherein the first, second, third, and fourth hash values each have 32 bits. 
     
     
         5 . The cryptographic hashing circuitry defined in  claim 1 , further comprising:
 a third register that stores a third hash value; and   a fourth register that stores a fourth hash value, wherein the logic circuitry is configured to generate the fourth hash value based on at least the stored third hash value and the logic circuitry is configured to generate the second hash value based on at least the stored first and third hash values, wherein the third register is configured to directly output the stored third hash value as part of the hash output value, wherein the fourth register is configured to output the stored fourth hash value as part of the hash output value, wherein the third hash value is different from the first and second hash values, and wherein the fourth hash value is different from the first, second, and third hash values.   
     
     
         6 . The cryptographic hashing circuitry defined in  claim 5 , further comprising:
 a fifth register that stores a fifth hash value, wherein the fifth register is configured to directly output the fifth hash value as part of the hash output value, and wherein the fifth hash value is different from the first, second, third, and fourth hash values; and   a sixth register that stores a sixth hash value, wherein the logic circuitry is configured to generate the third hash value based at least on the stored sixth hash value, wherein the logic circuitry is configured to generate the first hash value based on at least the stored fifth and sixth hash values, wherein the sixth register is configured to directly output the sixth hash value as part of the hash output value, and wherein the sixth hash value is different from the first, second, third, fourth, and fifth hash values.   
     
     
         7 . The cryptographic hashing circuitry defined in  claim 6 , further comprising:
 a seventh register that stores a seventh hash value, wherein the seventh register is configured to directly output the seventh hash value as part of the hash output value, and wherein the seventh hash value is different from the first, second, third, fourth, fifth, and sixth hash values; and   an eighth register that stores an eighth hash value, wherein the logic circuitry is configured to generate the sixth hash value based at least on the stored eighth hash value, wherein the logic circuitry is configured to generate the fifth hash value based at least on the stored seventh and eighth hash values, wherein the eighth register is configured to directly output the eighth hash value as part of the hash output value, and wherein the eighth hash value is different from the first, second, third, fourth, fifth, sixth, and seventh hash values.   
     
     
         8 . The cryptographic hashing circuitry defined in  claim 7 , wherein the hash output value comprises a 256-bit value and the first, second, third, fourth, fifth, sixth, seventh, and eighth hash values in the hash output value each have 32 bits. 
     
     
         9 . The cryptographic hashing circuitry defined in  claim 1 , wherein the logic circuitry receives a 32-bit message word from message scheduling circuitry and is configured to generate the second hash value based at least on the stored first hash value and the received 32-bit message word. 
     
     
         10 . The cryptographic hashing circuitry defined in  claim 1 , wherein the cryptographic hashing circuitry comprises Secure Hash Algorithm 256 (SHA-256) circuitry that is configured to perform sixty-four rounds of a SHA-256 hashing algorithm, and wherein the first and second hash registers are used to perform two of the sixty-four rounds of the SHA-256 hashing algorithm. 
     
     
         11 . The cryptographic hashing circuitry defined in  claim 10 , wherein the cryptographic hashing circuitry is configured to provide the hash output value to difficulty comparison circuitry that compares the hash output value to a predetermined difficulty value in accordance with a Bitcoin protocol. 
     
     
         12 . The cryptographic hashing circuitry defined in  claim 1 , wherein the hash output value comprises a final hash value output from the cryptographic hashing circuitry. 
     
     
         13 . The cryptographic hashing circuitry defined in  claim 1 , wherein the hash output value comprises an intermediate working value that is used to generate a final hash value output from the cryptographic hashing circuitry. 
     
     
         14 . An integrated circuit, comprising:
 hashing circuitry configured to perform a plurality of sequential rounds of a cryptographic hashing algorithm based on an initial hash value and a plurality of message words;   a message register that is configured to store the plurality of message words; and   control circuitry, wherein the control circuitry is configured to selectively route the plurality of message words from the message register to the hashing circuitry.   
     
     
         15 . The integrated circuit defined in  claim 14 , wherein the control circuitry is configured to selectively route the plurality of message words by sequentially routing selected message words of the plurality of message words from the message register to the hashing circuitry. 
     
     
         16 . The integrated circuit defined in  claim 14 , wherein the control circuitry is configured to selectively route the plurality of message words by providing the message register with a plurality of read pointers and a write pointer. 
     
     
         17 . The integrated circuit defined in  claim 16 , wherein the control circuitry is configured to read a subset of the plurality of message words from the message register using the plurality of read pointers, is configured to generate a new message word based on the read subset of the plurality of message words, and is configured to write the new message word to the message register using the write pointer. 
     
     
         18 . The integrated circuit defined in  claim 17 , wherein the control circuitry is configured to increment the plurality of read pointers and the write pointer after reading the subset of the plurality of message words from the message register and prior to writing the new message word to the message register. 
     
     
         19 . The integrated circuit defined in  claim 14 , further comprising:
 an additional message register that is configured to store an additional plurality of message words, wherein the control circuitry is configured to selectively route the additional plurality of message words from the additional message register to the hashing circuitry.   
     
     
         20 . The integrated circuit defined in  claim 19 , further comprising:
 at least one pipeline register that partitions the hashing circuitry into at least first and second groups of hashing circuits, wherein the first group of hashing circuits is configured to perform a first subset of the plurality of sequential rounds of the cryptographic hashing algorithm based on the plurality of message words, wherein the second group of hashing circuits is configured to perform a second subset of the plurality of sequential rounds of the cryptographic hashing algorithm based on the additional plurality of message words and an output of the pipeline register, wherein the control circuitry is configured to selectively route the plurality of message words from the message register to the first group of hashing circuits, and wherein the control circuitry is configured to selectively route the additional plurality of message words from the additional message register to the second group of hashing circuits.   
     
     
         21 . The integrated circuit defined in  claim 20 , wherein the cryptographic hashing algorithm comprises a Secure Hash Algorithm 256 (SHA-256) algorithm having sixty four sequential rounds, wherein the first subset of the plurality of sequential hashing rounds comprises a first sixteen of the sixty four sequential rounds, and wherein the second subset of the plurality of sequential hashing rounds comprises a second sixteen of the sixty four sequential rounds. 
     
     
         22 . The integrated circuit defined in  claim 20 , wherein the at least one pipeline register, the message register, and the additional message register are clocked using a clock signal having a common frequency. 
     
     
         23 . The integrated circuit defined in  claim 14 , wherein the message register receives and stores a message and wherein the control circuitry selectively routes portions of the stored message as the plurality of message words from the message register to the hashing circuitry. 
     
     
         24 . The integrated circuit defined in  claim 23 , wherein the message is a 512-bit message and each message word of the plurality of message words is a 32-bit message word. 
     
     
         25 . The integrated circuit defined in  claim 23 , further comprising:
 an additional message register, wherein the message register is configured to provide the stored message to the additional message register after the plurality of message words have been routed to the hashing circuitry, and wherein the control circuitry is configured to selectively route the plurality of message words from the additional message register to the hashing circuitry.   
     
     
         26 . An electronic device that forms a node in a peer-to-peer network of nodes that support transactions in a digital currency, the electronic device comprising:
 hashing circuitry configured to perform a plurality of sequential rounds of a Secure Hash Algorithm 256 (SHA-256) cryptographic hashing algorithm based at least on an initial hash value and a plurality of message words;   a memory array that is configured to store the plurality of message words; and   control circuitry, wherein the control circuitry is configured to selectively route the plurality of message words from the memory array to the hashing circuitry.   
     
     
         27 . The electronic device defined in  claim 26 , wherein the hashing circuitry comprises:
 a first group of hashing circuits that are configured to perform the plurality of sequential rounds of the SHA-256 cryptographic hashing algorithm based on the initial hash value and the plurality of message words; and   a second group of hashing circuits that are configured to perform an additional plurality of sequential rounds of the SHA-256 cryptographic hashing algorithm based on an output of the first group of hashing circuits and an additional plurality of message words, wherein the memory array is further configured to store the additional plurality of message words, and wherein the control circuitry is configured to selectively route the additional plurality of message words from the memory array to the second group of hashing circuits.   
     
     
         28 . The electronic device defined in  claim 27 , wherein the memory array comprises a plurality of memory elements arranged in rows and columns and wherein the control circuitry is configured to selectively route the additional plurality of message words and the plurality of message words by providing row and column pointers to the memory array. 
     
     
         29 . The electronic device defined in  claim 27 , further comprising:
 an additional memory array that is configured to store the plurality of message words and the additional plurality of message words, wherein the control circuitry is configured to selectively route the plurality of message words from the memory array to the first group of hashing circuits concurrently with selectively routing the plurality of additional message words from the additional memory array to the second group of hashing circuits.   
     
     
         30 . The electronic device defined in  claim 29 , further comprising:
 a pipeline register interposed between the first and second groups of hashing circuits; and   switching circuitry coupled between the memory array, the additional memory array, and the hashing circuitry, wherein the control circuitry is configured to control the switching circuitry to selectively route the plurality of message words and the additional plurality of message words between the memory array, the additional memory array, and the hashing circuitry.