Memory system and soc including linear addresss remapping logic

Abstract

A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

1 . (canceled) . 
     
     
         2 . A memory channel interleaving method for a power reduction or a performance improvement, the method comprising:
 remapping a memory access address for two or more memory devices accessed via two or more respective memory ports with an interleaving access area and a linear access area, the interleaving access area comprising memory addresses for an interleaving access operation for the performance improvement, the linear access area comprising memory addresses for a linear access operation for the power reduction;   receiving a signal that includes a power reduction mode or a performance improvement mode; and   performing the interleaving access operation or the linear access operation according to the performance improvement mode or the power reduction mode.   
     
     
         3 . The method of  claim 2 , wherein the linear access area comprises a first address range associated with a first memory device among the two or more memory devices and accessed via a first port among the two or more memory ports, and a second address range associated with a second memory device among the two or more memory devices and accessed via a second port among the two or more memory ports. 
     
     
         4 . The method of  claim 3 , wherein the performing the linear access operation comprises using the first address range associated with the first memory device while the second memory device is placed in the power reduction mode. 
     
     
         5 . The method of  claim 4 , further comprising when a last memory address in the first address range of the linear access area is reached:
 placing the first memory device in the power reduction mode;   activating the second memory device; and   performing the linear access operation in the power reduction mode for the second address range associated with the second memory device.   
     
     
         6 . The method of  claim 2 , wherein the linear access operation is performed in the linear access area with a first memory device among the two or more memory devices activated and a second memory device among the two or more memory devices placed in the power reduction mode. 
     
     
         7 . The method of  claim 2 , wherein the power reduction mode or the performance improvement mode is specified by the signal to a linear address remapping logic. 
     
     
         8 . The method of  claim 2 , wherein the interleaving access area or the linear access area comprises a bit specifying a memory device. 
     
     
         9 . The method of  claim 2 , wherein the two or more memory devices comprise dynamic random access memory (DRAM) devices. 
     
     
         10 . The method of  claim 2 , wherein a memory controller receives the signal that includes the power reduction mode or the performance improvement mode via a bus connection unit. 
     
     
         11 . The method of  claim 2 , further comprising adjusting a bandwidth balance among the two or more memory devices through the interleaving access operation. 
     
     
         12 . The method of  claim 2 , wherein when a memory dynamics is required, the linear access operation is performed. 
     
     
         13 . A memory channel interleaving system for a power reduction or a performance improvement, the system comprising:
 a linear address remapping logic configured to remap a memory access address for two or more memory devices accessed via two or more respective memory ports with an interleaving access area and a linear access area, the interleaving access area comprising memory addresses for an interleaving access operation for the performance improvement, the linear access area comprising memory addresses for a linear access operation for the power reduction, a linear address remapping logic being configured to receive a signal that includes a power reduction mode or a performance improvement mode; and   a memory controller configured to perform the interleaving access operation or the linear access operation according to the performance improvement mode or the power reduction mode.   
     
     
         14 . The system of  claim 13 , wherein the linear access area comprises a first address range associated with a first memory device among the two or more memory devices and accessed via a first port among the two or more memory ports, and a second address range associated with a second memory device among the two or more memory devices and accessed via a second port among the two or more memory ports. 
     
     
         15 . The system of  claim 14 , wherein the memory controller is configured to use the first address range associated with the first memory device while the second memory device is placed in the power reduction mode. 
     
     
         16 . The system of  claim 15 , wherein when a last memory address in the first address range of the linear access area is reached, the memory controller is configured to:
 place the first memory device in the power reduction mode;   activate the second memory device; and   perform the linear access operation in the power reduction mode for the second address range associated with the second memory device.   
     
     
         17 . The system of  claim 13 , wherein the linear access operation is performed in the linear access area with a first memory device among the two or more memory devices activated and a second memory device among the two or more memory devices placed in the power reduction mode. 
     
     
         18 . The system of  claim 13 , wherein the power reduction mode or the performance improvement mode is specified by the signal to the linear address remapping logic. 
     
     
         19 . The system of  claim 13 , wherein the interleaving access area or the linear access area comprises a bit specifying a memory device. 
     
     
         20 . The system of  claim 13 , wherein the two or more memory devices comprise dynamic random access memory (DRAM) devices. 
     
     
         21 . The system of  claim 13 , wherein the memory controller receives the signal that includes the power reduction mode or the performance improvement mode via a bus connection unit. 
     
     
         22 . The system of  claim 13 , wherein a bandwidth balance among the two or more memory devices is adjusted through the interleaving access operation. 
     
     
         23 . The system of  claim 13 , wherein when a memory dynamics is required, the linear access operation is performed. 
     
     
         24 . A system for providing a memory channel interleaving for a power reduction or a performance improvement, the system comprising:
 a system on chip (SOC) comprising linear address remapping logic configured to remap a memory access address for two or more memory devices accessed via two or more respective memory ports with an interleaving access area and a linear access area, the interleaving access area comprising memory addresses for an interleaving access operation for the performance improvement, the linear access area comprising memory addresses for a linear access operation for the power reduction, a linear address remapping logic being configured to receive a signal that includes a power reduction mode or a performance improvement mode; and   a memory controller residing on the SoC and configured to perform the interleaving access operation or the linear access operation according to the performance improvement mode or the power reduction mode.   
     
     
         25 . The system of  claim 24 , wherein the linear access area comprises a first address range associated with a first memory device among the two or more memory devices and accessed via a first port among the two or more memory ports, and a second address range associated with a second memory device among the two or more memory devices and accessed via a second port among the two or more memory ports. 
     
     
         26 . The system of  claim 25 , wherein the memory controller is configured to use the first address range associated with the first memory device while the second memory device is placed in the power reduction mode. 
     
     
         27 . The system of  claim 26 , wherein when a last memory address in the first address range of the linear access area is reached, the memory controller is configured to:
 place the first memory device in the power reduction mode;   activate the second memory device; and   perform the linear access operation in the power reduction mode for the second address range associated with the second memory device.   
     
     
         28 . The system of  claim 24 , wherein the linear access operation is performed in the linear access area with a first memory device among the two or more memory devices activated and a second memory device among the two or more memory devices placed in the power reduction mode. 
     
     
         29 . The system of  claim 24 , wherein the power reduction mode or the performance improvement mode is specified by the signal to the linear address remapping logic. 
     
     
         30 . The system of  claim 24 , wherein the interleaving access area or the linear access area comprises a bit specifying a memory device. 
     
     
         31 . The system of  claim 24 , wherein the two or more memory devices comprise dynamic random access memory (DRAM) devices. 
     
     
         32 . The system of  claim 24 , wherein the SOC resides on a portable communications device. 
     
     
         33 . The system of  claim 24 , wherein a bandwidth balance among the two or more memory devices is adjusted through the interleaving access operation. 
     
     
         34 . The system of  claim 24 , wherein when a memory dynamics is required, the linear access operation is performed.