Low power memory device

Abstract

A memory device includes a memory cell unit, a bit line unit and a buffering unit. The memory cell unit includes a plurality of memory cell groups. Each memory cell group includes at least one memory cell for storing data therein. The bit line unit includes a plurality of first bit lines each coupled to the at least one memory cell of a respective memory cell group, and a second bit line for transmitting to-be-read data. The buffering unit includes a plurality of two-state buffers. Each two-state buffer has an input terminal coupled to a respective first bit line, and an output terminal coupled to the second bit line. The memory device does not require a sense amplifier, and thus consumes relatively small power. The memory device can operate at a relatively high frequency when properly configured.

1 . A memory device comprising:
 a memory cell unit including a plurality of memory cell groups, each of said memory cell groups including at least one memory cell for storing data therein;   a bit line unit including a plurality of first bit lines, each of which is coupled to said at least one memory cell of a respective one of said memory cell groups, and a second bit line for transmitting to-be-read data; and   a buffering unit including a plurality of two-state buffers, each of said two-state buffers having an input terminal coupled to a respective one of said first bit lines, and an output terminal coupled to said second bit line, each of said two-state buffers being operable between an output enable state and an output disable state based on a voltage at said input terminal, and outputting a predetermined reference voltage at said output terminal when operating in the output enable state.   
     
     
         2 . The memory device of  claim 1 , wherein each of said two-state buffers is a transistor that has a first terminal for receiving the predetermined reference voltage, a second terminal serving as said output terminal, and a control terminal serving as said input terminal. 
     
     
         3 . The memory device of  claim 1 , wherein each of said two-state buffers is a field effect transistor that has a source terminal, a drain terminal and a gate terminal, one of said source and drain terminals receiving the predetermined reference voltage, the other of said source and drain terminals serving as said output terminal, said gate terminal serving as said input terminal. 
     
     
         4 . The memory device of  claim 1 , further comprising a biasing unit that is coupled to said input terminal of each of said two-state buffers for supplying a predetermined bias voltage thereto. 
     
     
         5 . The memory device of  claim 1 , further comprising a biasing unit that is coupled to said second bit line for supplying a predetermined bias voltage thereto. 
     
     
         6 . The memory device of  claim 1 , wherein each of said memory cell groups further includes a dummy cell that is coupled to a respective one of said first bit lines for supplying a predetermined bias voltage thereto. 
     
     
         7 . The memory device of  claim 1 , wherein one of said at least one memory cell of each of said memory cell groups outputs the data stored therein to bias a corresponding one of said first bit lines. 
     
     
         8 . The memory device of  claim 1 , further comprising a plurality of switches, each of said switches being coupled between said input terminal of a respective one of said two-state buffers and a respective one of said first bit lines. 
     
     
         9 . The memory device of  claim 1 , further comprising a plurality of switches, each of said switches being coupled between said output terminal of a respective one of said two-state buffers and said second bit line. 
     
     
         10 . The memory device of  claim 1 , wherein said bit line unit further includes a third bit line that is coupled to said at least one memory cell of each of said memory cell groups and that transmits to-be-written data. 
     
     
         11 . The memory device of  claim 1 , further comprising a plurality of switches;
 wherein said bit line unit further includes a third bit line for transmitting to-be-written data, and a plurality of fourth bit lines, each of which is coupled to said at least one memory cell of a respective one of said memory cell groups; and   wherein each of said switches is coupled between said third bit line and a respective one of said fourth bit lines.   
     
     
         12 . The memory device of  claim 1 , further comprising a plurality of switches;
 wherein each of said switches is coupled between a respective one of said first bit lines and said second bit line; and   wherein said second bit line further transmits to-be-written data.   
     
     
         13 - 21 . (canceled)