Vertical cell-type semiconductor device having protective pattern

Abstract

According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

1 .- 20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 a substrate;   a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, the stacked structure defining a through-hole, each of the gate electrodes including a portion in which a vertical width thereof is reduced with the approach to one end thereof;   blocking layers between the interlayer insulating layers and the gate electrodes; and   a vertical structure in the through-hole, the vertical structure including a gap-fill pattern in a middle of the through-hole, a channel pattern surrounding an outer surface of the gap-fill pattern, and a gate dielectric layer surrounding an outer surface of the channel pattern,   wherein the gate dielectric layer includes a tunneling layer in contact with the channel pattern, a charge trap layer in contact with the tunneling layer, a barrier layer in contact with the charge trap layer, and protective patterns being between the barrier layer and one of the gate electrodes, each one of the protective patterns extending between two of the interlayer insulating layers, and   wherein the protective patterns include an oxide of silicon.   
     
     
         22 . The semiconductor device of  claim 21 , wherein the blocking layers includes a dielectric material having a metal. 
     
     
         23 . The semiconductor device of  claim 22 , wherein the blocking layers include aluminum oxide or hafnium oxide. 
     
     
         24 . The semiconductor device of  claim 21 , wherein the protective patterns is a higher density than the barrier layer. 
     
     
         25 . The semiconductor device of  claim 21 , wherein each of the portions of the gate electrodes includes an upper inclined surface and a lower inclined surface opposite to the upper inclined surface, and
 wherein each one of the protective patterns extends between one of the interlayer insulating layers and the upper inclined surface of the portion of one of the gate electrodes, and between one of the interlayer insulating layers and the lower inclined surface of the portion of one of the gate electrodes.   
     
     
         26 . The semiconductor device of  claim 25 , wherein each of the gate electrode further includes an upper surface opposite to a lower surface, and
 wherein the blocking layers extends between one of the interlayer insulating layer and the upper surface of one of the gate electrodes, and between one of the interlayer insulating layer and the lower surface of one of the gate electrode.   
     
     
         27 . The semiconductor device of  claim 21 , wherein each one of the protective patterns includes a protrusion protruding into the through-hole. 
     
     
         28 . The semiconductor device of  claim 27 , wherein the barrier layer contacts exposed lateral surfaces of the interlayer insulating layers, and the protrusions of the protective patterns. 
     
     
         29 . The semiconductor device of  claim 21 , wherein a horizontal distance between the portion of one of the gate electrodes and the channel layer is greater than a horizontal distance between the channel layer to one of the interlayer insulating layers. 
     
     
         30 . The semiconductor device of  claim 21 , further comprising:
 a contact electrode on the gap-fill pattern and contacting the channel pattern.   
     
     
         31 . The semiconductor device of  claim 30 , further comprising:
 capping layers on the stacked structure, wherein the capping layers define a hole exposing an upper surface of the contact electrode.   
     
     
         32 . The semiconductor device of  claim 31 , further comprising:
 a conductive interconnection on the capping layers, wherein the conductive interconnection is electrically connected to the exposed upper surface of the contact electrode.   
     
     
         33 . A semiconductor device, comprising:
 a substrate;   a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, the stacked structure defining a through-hole, each of the gate electrodes including a portion in which a vertical width thereof is reduced with the approach to one end thereof;   blocking layers between the interlayer insulating layers and the gate electrodes;   a gap-fill pattern in a middle of the through-hole;   a channel pattern surrounding an outer surface of the gap-fill pattern; and   a gate dielectric layer between the stacked structure and the channel pattern, the gate dielectric layer includes a tunneling layer in contact with the channel pattern, a charge trap layer in contact with the tunneling layer, a protective layer in contact with the charge trap layer, protective patterns that are integral with the protective layer, the protective patterns extending to the gate electrodes.   
     
     
         34 . The semiconductor device of  claim 33 , wherein each of the blocking layers extends between the gate electrodes and the gate dielectric layer. 
     
     
         35 . The semiconductor device of  claim 33 , wherein
 the protective patterns include an oxide of silicon,   the charge trap layer includes one of silicon nitride, aluminum oxide, zirconium oxide, hafnium oxide, lanthanum oxide, and   the tunneling layer includes one of silicon oxide and nitrogen-doped silicon oxide.   
     
     
         36 . A semiconductor device, comprising:
 a substrate;   interlayer insulating layers on the substrate;   gate electrodes between the interlayer insulating layers, each of the gate electrode including a first portion having a first lateral surface, and a second portion having a second lateral surface opposite to the first lateral surface, a length of the first lateral surface being shorter than a length of the second lateral surface;   blocking layers between the interlayer insulating layers and the second portions of the gate electrodes;   a channel pattern on the first portions of the gate electrodes, the channel pattern extending on lateral surfaces of the interlayer insulating layers; and   a gate dielectric layer extending vertically over the substrate between interlayer insulating layers and the channel pattern, the gate dielectric layer including protective patterns between the channel pattern and the blocking layers, the protective patterns extending between the interlayer insulating layers and the first portions of the gate electrodes.   
     
     
         37 . The semiconductor device of  claim 36 , wherein the first portions of the gate electrodes each have a thickness that gradually reduces from the second portions of the gate electrodes towards the gate dielectric layer. 
     
     
         38 . The semiconductor device of  claim 36 , wherein
 the protective patterns include an oxide of silicon,   the interlayer insulating layers include an oxide, and   the oxide of silicon in the protective patterns is more compact than the oxide of the interlayer insulating layers.   
     
     
         39 . The semiconductor device of  claim 36 , further comprising:
 a protective layer that extends vertically over the substrate, the protective layer extending between the gate dielectric layer and the protective patterns, and between the interlayer insulating layer and the gate dielectric layer.   
     
     
         40 . The semiconductor device of  claim 39 , wherein a material of the protective layer is the same as a material of the protective patterns.