Charge ordered vertical transistors

Abstract

A vertical charge ordered transistor is disclosed. A thin charge ordered layer is employed as a tunnel barrier between two electrodes. A gate-induced accumulation of charge destabilizes the charge ordered state around the circumference of the device, opening up a parallel ohmic conduction channel, which leads to an exponential increase in source-drain current. VCOT devices have the potential to exhibit very large on/off ratios, low off-state currents, and sub-threshold slopes below 60 mV/dec.

1 . A vertical charge ordered transistor comprising:
 a charge ordered layer;   a source layer located adjacent the charge ordered layer;   a drain layer located adjacent the charge ordered layer;   a gate located adjacent to at least one of the layers; and   a source electrode located on the source layer and a drain electrode located on the drain layer.   
     
     
         2 . The vertical charge ordered transistor of  claim 1 , wherein the gate comprises a gate electrode and a gate dielectric. 
     
     
         3 . The vertical charge ordered transistor of  claim 1 , wherein the source layer is made from a perovskite material 
     
     
         4 . The vertical charge ordered transistor of  claim 3 , wherein the drain layer is made from a perovskite materials. 
     
     
         5 . The vertical charge ordered transistor of  claim 3  wherein the source layer material is selected from the group of materials consisting of LaNiO 3 , La 2/3 Sr 1/3 MnO 3 , and SrRuO 3 . 
     
     
         6 . The vertical charge ordered transistor of  claim 5 , wherein the drain layer material is selected from the group of materials consisting of LaNiO 3 , La 2/3 Sr 1/3 MnO 3 , and SrRuO 3 . 
     
     
         7 . The vertical charge ordered transistor of  claim 1 , wherein the charge ordered layer is made from La 1/3 Sr 2/3 FeO 3 . 
     
     
         8 . A method of making a vertical charge ordered transistor comprising:
 forming a charge ordered layer using an adjacent structural imprinting layer;   forming a source layer located adjacent the charge ordered layer;   forming a drain layer located adjacent the charge ordered layer;   forming a gate located adjacent to at least one of the layers; and   placing a source electrode located on the source layer and a drain electrode located on the drain layer.   
     
     
         9 . The method of  claim 8 , wherein the gate comprises a gate electrode and a gate dielectric. 
     
     
         10 . The method of  claim 8 , wherein the source layer is formed from a perovkite material. 
     
     
         11 . The method of  claim 10 , wherein the drain layer is formed from a perovskite materials. 
     
     
         12 . The method of  claim 10 , wherein the source layer material is formed from the group of materials consisting of LaNiO 3 , La 2/3 Sr 1/3 MnO 3 , and SrRuO 3 . 
     
     
         13 . The method of  claim 11 , wherein the drain layer material is formed from the group of materials consisting of LaNiO 3 , La 2/3 Sr 1/3 MnO 3 , and SrRuO 3 . 
     
     
         14 . The method of  claim 8 , wherein the charge ordered layer is made from La 1/3 Sr 2/3 FeO 3 . 
     
     
         15 . A vertical charge ordered transistor comprising:
 a charge ordered layer;   a source layer located adjacent the charge ordered layer;   a drain layer located adjacent the charge ordered layer;   a gate located adjacent to at least one of the layers;   a source electrode and a drain electrode; and   wherein the source layer and the drain layer imprint the charge ordered layer.   
     
     
         16 . The vertical charge ordered transistor of  claim 15 , wherein the gate comprises a gate electrode and a gate dielectric. 
     
     
         17 . The vertical charge ordered transistor of  claim 15 , wherein the source layer is made from a peroskovite material. 
     
     
         18 . The vertical charge ordered transistor of  claim 17 , wherein the drain layer is made from a peroskovite materials. 
     
     
         19 . The vertical charge ordered transistor of  claim 17 , wherein the source layer material is selected from the group of materials consisting of LaNiO 3 , La 2/3 Sr 1/3 MnO 3 , and SrRuO 3 . 
     
     
         20 . The vertical charge ordered transistor of  claim 19 , wherein the drain layer material is selected from the group of materials consisting of LaNiO 3 , La 2/3 Sr 1/3 MnO 3 , and SrRuO 3 . 
     
     
         21 . (canceled)