US2016163652A1PendingUtilityA1

Coated fullerenes, composites and dielectrics made therefrom

49
Assignee: BARRON ANDREW RPriority: Nov 20, 2001Filed: Feb 12, 2016Published: Jun 9, 2016
Est. expiryNov 20, 2021(expired)· nominal 20-yr term from priority
H10W 20/4462H10W 20/031C09C 1/3045Y10T428/30C04B 35/62807C01B 2202/02C04B 2235/5288C01P 2004/03C01P 2004/32C01B 2202/28C01P 2004/04B82Y 40/00C01B 32/168C01P 2002/54C08K 9/02C01B 32/156C01P 2006/40B82Y 30/00C01B 2202/06C09C 1/44C01P 2004/12C01P 2004/84C01P 2004/13C01B 32/174H01L 21/76838C01B 31/0253H01L 23/53276C01B 31/0213B82Y 10/00H10K 85/211H10K 85/615H10K 85/221
49
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

The present invention relates to coated fullerenes comprising a layer of at least one inorganic material covering at least a portion of at least one surface of a fullerene and methods for making. The present invention further relates to composites comprising the coated fullerenes of the present invention and further comprising polymers, ceramics, and/or inorganic oxides. A coated fullerene interconnect device where at least two fullerenes are contacting each other to form a spontaneous interconnect is also disclosed as well as methods of making. In addition, dielectric films comprising the coated fullerenes of the present invention and methods of making are further disclosed.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of making a coated fullerene interconnect device comprising a layer of at least one inorganic material covering at least a portion of at least one surface of fullerenes wherein:
 at least two fullerenes are contacting each other to form a spontaneous interconnect; and at least one suitable metal contact is found at the site of at least one spontaneous interconnect, wherein said method comprises:   (a) dispersing a fullerene under suitable conditions to provide a dispersed fullerene;   (b) depositing at least one inorganic material under suitable conditions onto at least one surface of the dispersed fullerene to provide a coated fullerene;   (c) isolating the coated fullerene;   (d) removing at least a portion of the layer of inorganic material in a manner suitable for permitting at least two fullerenes to contact each other to provide at least one spontaneous interconnect;   (e) optionally, allowing at least two fullerenes of a spontaneous interconnect to separate;   (f) optionally, allowing at least two fullerenes to contact each other to provide at least one new spontaneous interconnect; and   (g) depositing a suitable metal contact at the site of at least one spontaneous interconnect and/or one new spontaneous interconnect.   
     
     
         2 . The method according to  claim 1 , wherein the fullerenes are selected from the group consisting of C 60 , C 72 , C 84 , C 96 , C 108 , C 120 , single-walled carbon nanotubes (SWNT), multi-walled carbon nanotubes (MWNT), and combinations thereof. 
     
     
         3 . The method according to  claim 2 , wherein the fullerenes are single-walled carbon nanotubes (SWNT). 
     
     
         4 . The method according to  claim 1 , wherein the at least one inorganic material comprises an inorganic oxide. 
     
     
         5 . The method according to  claim 4 , wherein the inorganic oxide is an oxide of silicon. 
     
     
         6 . The method according to  claim 1 , wherein the fullerene is dispersed by a technique of chemical functionalization or surfactant addition. 
     
     
         7 . The method according to  claim 1 , wherein removing the at least a portion of the layer of inorganic material comprises treatment with a suitable etchant. 
     
     
         8 . The method according to  claim 1 , wherein removing the at least a portion of the layer of inorganic material is effective in removing all of the inorganic material. 
     
     
         9 . The method according to  claim 1 , wherein removing the at least a portion of the layer of inorganic material in a suitable manner comprises selectively removing inorganic material from the ends of the fullerenes. 
     
     
         10 . The method according to  claim 1 , wherein removing the at least a portion of the layer of inorganic material in a suitable manner comprises selectively removing inorganic material from the central portion of the fullerenes. 
     
     
         11 . The method according to  claim 1 , wherein separating the at least one spontaneous interconnect comprises treatment with a suitable surfactant. 
     
     
         12 . The method according to  claim 1 , wherein the method further comprises testing the coated fullerene interconnect devices for suitability as electronic devices. 
     
     
         13 . A coated fullerene interconnect device made according to the method of  claim 1 . 
     
     
         14 . A coated fullerene interconnect device comprising:
 a layer of at least one inorganic material covering at least a portion of at least one surface of fullerenes, wherein at least two fullerenes are contacting each other to form a spontaneous interconnect; and   at least one suitable metal contact is found at the site of at least one spontaneous interconnect.   
     
     
         15 . The coated fullerene interconnect device according to  claim 14 , wherein the device performs some electronic switching function. 
     
     
         16 . The coated fullerene interconnect device according to  claim 14 , wherein the device performs some electronic memory function. 
     
     
         17 . The coated fullerene interconnect device according to  claim 14 , wherein the device performs some electronic sensory function. 
     
     
         18 . A method of depositing a dielectric onto a silicon computer chip comprising a coated fullerene comprising:
 a layer of at least one inorganic material covering at least a portion of at least one surface of a fullerene onto a computer chip, wherein the method comprises   contacting a solution comprising coated fullerene with at least one region of a computer chip in a manner effective for depositing a dielectric layer to said region.   
     
     
         19 . The method according to  claim 18 , wherein contacting a solution comprising coated fullerene with at least one region of a computer chip in an effective manner takes place at a temperature no greater than 50° C. 
     
     
         20 . The method according to  claim 18 , wherein the dielectric layer is uniform in thickness. 
     
     
         21 . The method according to  claim 18 , wherein contacting a solution comprising coated fullerene with at least one region of a computer chip in an effective manner comprises effecting control over the void volume.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.