Semiconductor device having fin-type field effect transistor and method of manufacturing the same

Abstract

A field effect transistor includes a fin structure, having a sidewall, protruding from a substrate, and a device isolation structure on the substrate, the device isolation structure defining the sidewall of the fin structure, wherein the fin structure includes a buffer semiconductor pattern disposed on the substrate and a channel pattern disposed on the buffer semiconductor pattern, wherein the buffer semiconductor pattern has a lattice constant different from that of the channel pattern, and wherein the device isolation structure includes a gap-fill insulating layer, and includes an oxidation blocking layer pattern disposed between the buffer semiconductor pattern and the gap-fill insulating layer.

1 - 29 . (canceled) 
     
     
         30 . A method of manufacturing a semiconductor device, the method comprising:
 forming a fin structure protruding from a substrate, the fin structure including a buffer semiconductor pattern and a channel pattern disposed on the buffer semiconductor pattern;   forming an oxidation blocking layer on a sidewall of the fin structure;   forming a preliminary gap-fill insulating layer on the oxidation blocking layer by using a flowable chemical vapor deposition (FCVD) process; and   annealing the preliminary gap-fill insulating layer to form a gap-fill insulating layer on the oxidation blocking layer.   
     
     
         31 . The method of  claim 30 , wherein the buffer semiconductor pattern has an oxidation rate greater than that of the channel pattern. 
     
     
         32 . The method of  claim 30 , further comprising forming a buffer oxide layer on a sidewall of the fin structure by using a thermal oxidation process before forming the oxidation blocking layer. 
     
     
         33 . The method of  claim 32 , wherein a portion of the buffer oxide layer is nitrided when annealing the preliminary gap-fill insulating layer. 
     
     
         34 . The method of  claim 30 , wherein annealing the preliminary gap-fill insulating layer is performed by using at least one process selected from the group consisting of a wet annealing process in a temperature range of about 500° C. to about 700° C. and a nitrogen annealing process in a temperature range of about 600° C. to about 800° C. 
     
     
         35 . The method of  claim 30 , further comprising:
 recessing the gap-fill insulating layer to expose a portion of the oxidation blocking layer; and   removing the exposed portion of the oxidation blocking layer to form an oxidation blocking layer pattern.   
     
     
         36 . The method of  claim 30 , wherein forming the preliminary gap-fill insulating layer comprises injecting a gas mixture containing a first precursor and a second precursor into a processing chamber, and
 wherein the first precursor includes silicon (Si) and the second precursor includes at least one selected from the group consisting of nitrogen, hydrogen, oxygen, and a mixture thereof.   
     
     
         37 . The method of  claim 30 , wherein the oxidation blocking layer obstructs oxygen movement from the preliminary gap-fill insulating layer to the buffer semiconductor pattern during the annealing step.