Apparatus system and method for identification of memory

Abstract

A system and method of identifying a memory includes detecting defects in regions of the memory, comparing the detected defects with defects contained in a previously-created defect map associated with the memory and stored in another memory of a device accessing the memory, confirming the identity of the memory where a result of the comparison indicates the detected defects match defects contained in the previously-created defect map; and denying the identity of the memory where the result of the comparison indicates the detected defects do not match the defects contained in the previously-created defect map.

What is claimed is: 
     
         1 . An apparatus for uniquely identifying a memory, comprising:
 an information handling system;   a first memory;   a communication port; and   a processor adapted to communicatively couple with a second memory, to detect defects in regions of the second memory, to store the detected defects as a defect map, to associate the defect map with the second memory, to store the associated defect map in the first memory, to use the stored associated defect map to subsequently uniquely identify the second memory, and to use the unique identification for security purposes between the second memory and the first memory.   
     
     
         2 . The apparatus of  claim 1 , wherein the processor is adapted to detect the defects in selected regions of the second memory, and locations of the selected regions are pre-determined. 
     
     
         3 . The apparatus of  claim 1 , wherein the stored defect map comprises a defect list of the second memory used in defect management of the second memory which the processor is adapted to copy and store in the second memory. 
     
     
         4 . The apparatus of  claim 1 , wherein the processor is adapted to encrypt the defect list prior to storing the defect list in the first memory. 
     
     
         5 . The apparatus of  claim 1 , wherein the second memory is one of a semiconductor memory, a magnetic memory, an optical memory, or a combination thereof. 
     
     
         6 . The apparatus of  claim 1 , further comprising:
 allowing a data exchange between the information handling system and the second memory where the identity of the second memory is confirmed; and   preventing the data exchange between the information handling system and the second memory where the identity of the second memory is denied.   
     
     
         7 . The apparatus of  claim 1 , wherein the processor is adapted to detect defects in regions of the second memory by writing a logical state to the second memory, and reading a different logical state than what was written. 
     
     
         8 . The apparatus of  claim 1 , wherein the processor is adapted to detect new defects in regions of the second memory and store an updated defect map. 
     
     
         9 . The apparatus of  claim 1 , wherein the defects in regions of the second memory are functional imperfections.