Operating method of storage device

Abstract

An operation method a storage device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory is provided. The operation method includes erasing memory cells of the nonvolatile memory using the memory controller and prohibiting an erase of the erased memory cells for a critical time using the memory controller.

What is claimed is: 
     
         1 . An operation method of a storage device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory, the operation method comprising:
 erasing memory cells of the nonvolatile memory using the memory controller; and   prohibiting an erase of the erased memory cells for a critical time using the memory controller.   
     
     
         2 . The operation method of  claim 1 , wherein the prohibiting the erase of the erased memory cells for the critical time includes:
 setting at least some memory cells among the erased memory cells to store valid data;   managing a table to indicate valid data is stored in the at least some memory cells; and   releasing the at least some memory cells after the critical time has elapsed.   
     
     
         3 . The operation method of  claim 2 , wherein the memory controller is configured to select the memory cells as an erase target when valid data is not stored in the memory cells. 
     
     
         4 . The operation method of  claim 1 , wherein the prohibiting the erase of the erased memory cells for the critical time includes:
 collecting information of memory blocks being erased among memory blocks of the nonvolatile memory; and   periodically registering the information collected in a slot of an interval table together with an initial count according to a period,   wherein each of the erased memory blocks is virtually set to store valid data.   
     
     
         5 . The operation method of  claim 4 , wherein the prohibiting the erase of the erased memory cells for the critical time further includes:
 periodically reducing counts corresponding to the slots of the interval table according to the period.   
     
     
         6 . The operation method of  claim 5 , wherein the prohibiting the erase of the erased memory cells for the critical time further includes:
 periodically releasing information of a slot having a count which reaches a threshold value among the slots of the interval table according to the period.   
     
     
         7 . The operation method of  claim 5 , wherein the prohibiting the erase of the erased memory cells for the critical time further includes:
 periodically releasing virtual settings of memory blocks corresponding to a slot having a count which reaches a threshold value among the slots of the interval table according to the period.   
     
     
         8 . The operation method of  claim 4 , wherein the prohibiting the erase of the erased memory cells for the critical time further includes mapping at least a part of physical addresses of each of the erased memory blocks to a logical address of an out-of-range area of a logical address of the storage device. 
     
     
         9 . The operation method of  claim 4 , further comprising:
 storing the interval table in the nonvolatile memory before power-off.   
     
     
         10 . The operation method of  claim 9 , further comprising:
 reading the interval table from the nonvolatile memory when power is turned on.   
     
     
         11 . An operation method of a storage device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory, the operation method comprising:
 programming memory cells of the nonvolatile memory using the memory controller; and   prohibiting an erase of the programmed memory cells for critical time using the memory controller.   
     
     
         12 . The operation method of  claim 11 , wherein the prohibiting the erase of the programmed memory cells for the critical time includes:
 setting at least some memory cells among the programmed memory cells to store valid data;   managing a table to indicate valid data is stored in the at least some memory cells; and   releasing the setting of at least some memory cells after the critical time has elapsed.   
     
     
         13 . The operation method of  claim 11 , wherein the prohibiting the erase of the programmed memory cells for the critical time includes:
 collecting information of memory blocks being programmed among memory blocks of the nonvolatile memory; and   periodically registering the information being collected in a slot of an interval table together with an initial count according to a period,   wherein each of the programmed memory blocks is virtually set to store valid data.   
     
     
         14 . The operation method of  claim 13 , wherein the collecting the information of memory blocks being programmed includes:
 collecting information of memory blocks in which last memory cells are programmed according to a program order of each memory block.   
     
     
         15 . The operation method of  claim 13 , wherein the collecting the information of memory blocks being programmed includes collecting information of memory blocks in which first memory cells are programmed according to a program order of each memory block. 
     
     
         16 . An operation method of a storage device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory, the nonvolatile memory including a plurality of memory cells, the operation method comprising:
 erasing the memory cells in one of a plurality of erase operation units of the nonvolatile memory using the memory controller; and at least one of:   excluding the memory cells in the one of the plurality of erase operation units as an available erase target for a critical period of time using the memory controller, the critical period of time being based on a time elapsed since the memory cells in the one of the plurality of erase operation units were last erased, and   programming at least some of the memory cells in the one of the plurality of erase operations units and inhibiting the memory cells in the one of the plurality of erase operation units from being erased for a critical length of time using the memory controller, the critical length of time being based on a time elapsed since the at some of the memory cells in the one of the plurality of erase operation units were last programmed.   
     
     
         17 . The operation method of  claim 16 , wherein
 the memory cells in the nonvolatile memory are organized into a plurality of blocks,   the memory blocks each include a plurality of physical pages,   the at least one of excluding the memory cells in the one of the plurality of erase operation units as the available erase target and programming at least some of the memory cells in the one of the plurality of erase operation units and inhibiting the memory cells in the one of the plurality of erase operation units from being erased from the critical length of time includes,
 managing a table using the memory controller that maps logical page addresses to the physical pages of the plurality of memory blocks, 
 mapping a virtual page to at least one of the physical pages included in the one of a plurality of erase operation units of the nonvolatile memory after the erasing the one of a plurality of erase operation units of the nonvolatile memory, 
 removing the virtual page mapping to the at least one of the physical pages included in the one of the plurality of erase operation units if one of the critical period of time and the critical length of time has elapsed since the mapping the virtual page, and 
 prohibiting the at least one of the plurality of erase operation units from being erased using the memory controller if any one of the physical pages included in the at least one of the plurality of erase operation units is mapped to the virtual page. 
   
     
     
         18 . The operation method of  claim 16 , wherein the at least one of excluding the memory cells in the one of the plurality of erase operation units as the available erase target for the critical period of time using the memory controller and programming the at least some of the memory cells in the one of the plurality of erase operations units and inhibiting the memory cells in the one of the plurality of erase operation units from being erased for the critical length of time using the memory controller is the excluding the memory cells in the one of the plurality of erase operation units as the available erase target for the critical period of time using the memory controller. 
     
     
         19 . The operation method of  claim 16 , wherein the at least one of excluding the memory cells in the one of the plurality of erase operation units as the available erase target for the critical period of time using the memory controller and the programming the at least some of the memory cells in the one of the plurality of erase operations units and inhibiting the memory cells in the one of the plurality of erase operation units from being erased for the critical length of time using the memory controller is the programming the at least some of the memory cells in the one of the plurality of erase operations units and inhibiting the memory cells in the one of the plurality of erase operation units from being erased for the critical length of time using the memory controller. 
     
     
         20 . The operation method of  claim 16 , wherein
 the memory cells in the nonvolatile memory are organized into a plurality of blocks,   each one of the plurality of blocks includes a plurality of strings, and   each one of the strings includes a number of the memory cells stacked on top of each other in a vertical direction between a ground selection transistor and a string selection transistor.