Semiconductor device and clock correction method

Abstract

A frequency error calculator includes a first logic circuit that receives a control signal and a clock, a second logic circuit that receives the control signal and a reference signal, a divider circuit that receives a logical product value of the control signal and the clock from the first logic circuit, and a counter that receives the logical product value of both the control signal and a reference signal. The divider circuit generates a divider signal that divides the clock and inputs the generated divider signal to the counter, the count value providing a calculation of a frequency error at a calculation timing specified by the control signal.

What is claimed is: 
     
         1 . A frequency error calculator, comprising:
 a first logic circuit that receives a control signal and a clock;   a second logic circuit that receives the control signal and a reference signal;   a divider circuit that receives a logical product value of the control signal and the clock from the first logic circuit; and   a counter that receives the logical product value of both the control signal and a reference signal,   wherein the divider circuit generates a divider signal that divides the clock and inputs the generated divider signal to the counter, the count value providing a calculation of a frequency error at a calculation timing specified by the control signal.   
     
     
         2 . The frequency error calculator according to  claim 1 , wherein the first logic circuit utilizes the control signal to mask the clock. 
     
     
         3 . The frequency error calculator according to  claim 1 , wherein the second logic circuit utilizes the control signal to mask the reference clock. 
     
     
         4 . The frequency error calculator according to  claim 1 , further comprising a count control circuit that outputs a permit signal allowing processing of the count from the counter when a high-level of the control signal is input. 
     
     
         5 . The frequency error calculator according to  claim 1 , wherein the counter utilizes the divider signal as an operation trigger, and processes the count using the reference clock as an operation clock. 
     
     
         6 . The frequency error calculator according to  claim 1 , wherein the counter counts the number of reference clock inputs in the period between the rising edge or falling edge of the divider signal and the next rising edge or falling edge. 
     
     
         7 . The frequency error calculator according to  claim 1 , wherein the counter counts the number of reference clock inputs during the multiple cycles of divider signal and calculates an average of the counts. 
     
     
         8 . The frequency error calculator according to  claim 1 , wherein the counter inputs a count value calculated in a count processing to an operation clock generator circuit and the control circuit. 
     
     
         9 . The frequency error calculator according to  claim 1 , wherein each of the first logic circuit and the second logic circuit comprise an AND logic.